Manufacturable and reliable fluorine-doped low-k interlayer dielectric process for high performance logic LSI

High-performance germanium-seeded laterally crystallized TFTs for vertical device integration

“…Numerous techniques are under consideration to decrease interconnect delay, including the use of low resistivity interconnect materials [1], lowdielectrics [2], and increased packing density using various techniques to increase the level of achievable integration for a given device generation. Of these, the increase of packing density using vertical integration of devices is particularly interesting, as it offers the additional benefits of decreasing block-level routing complexity (through the ability to layer blocks) and dramatically decreasing the consumed silicon realestate.…”