High-performance germanium-seeded laterally crystallized TFTs for vertical device integration

Abstract

Abstract-Increasing chip complexity and area has resulted in interconnect delay becoming a significant fraction of overall chip delay. Continued scaling of design rules will further aggravate this problem. Vertical integration of devices will enable a substantial reduction in chip size and thus in interconnect delay. We present a novel technique to achieve vertical integration of CMOS devices. Germanium is used as a seeding agent at the source and/or drain of thin film transistors (TFT's) to laterally crystallize amorphous silicon films, resulting in high-performance devices. This is achieved through the formation of large grain polysilicon with a precise control over the location of the grain. TFT's have been demonstrated offering substantial performance improvement over conventional unseeded polycrystalline TFT's, with demonstrated mobilities as high as 300 cm 2 /V-s. The process is fully CMOS compatible and has a low thermal budget. It is highly scalable to deep-submicron technologies and, with suitable optimization, should enable the production of high-performance, high density, vertically integrated ULSI.

Mechanism of Germanium-Induced Perimeter Crystallization of Amorphous Silicon

“…Ge-seeded lateral crystallization of ␣-Si was originally proposed by Subramanian et al 12,13 to exploit the long incubation time of nucleated grains to achieve lateral crystallization. It was reported that Ge introduces an additional nucleation site by the formation of a SiGe layer at the Ge-Si interface which crystallizes faster than pure Si at any given temperature.…”

“…12,13 In a previous article, we reported a new low-temperature ͑500°C͒ ␣-Si crystallization phenomenon that occurs at the perimeter of a Ge layer grown on ␣-Si through a window in a SiO 2 layer.…”

“…The lower melting point of germanium than silicon was reported to reduce the incubation time for the crystallization of the underlying amorphous silicon film by the formation of a SiGe layer at the Ge-Si interface. 12,13 Improved values of mobility were obtained for thin-film transistors fabricated in ␣-Si layers crystallized using a germanium seed. 12,13 In a previous article, we reported a new low-temperature ͑500°C͒ ␣-Si crystallization phenomenon that occurs at the perimeter of a Ge layer grown on ␣-Si through a window in a SiO 2 layer.…”

“…12,13 Improved values of mobility were obtained for thin-film transistors fabricated in ␣-Si layers crystallized using a germanium seed. 12,13 In a previous article, we reported a new low-temperature ͑500°C͒ ␣-Si crystallization phenomenon that occurs at the perimeter of a Ge layer grown on ␣-Si through a window in a SiO 2 layer. 14 This phenomenon was termed perimeter crystallization and the results suggested the presence of an additional crystallization mechanism in the early stages of the crystallization process.…”

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

“…For the devices on the upper planes, however, different fabrication methods are required. Several techniques, based on laser recrystallization [41] or seed crystallization [42], are used to produce CMOS or SOI devices on the upper planes.…”