Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing

Zaruba, Florian; Schuiki, Fabian; Benini, Luca

doi:10.1109/mm.2020.3045564

Cited by 39 publications

(33 citation statements)

References 8 publications

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“…The Manticore architecture [14] is a state-of-the-art manycore processor for high-performance, high-efficiency, dataparallel floating-point computing. A Manticore accelerator consists of four chiplet dies on an interposer.…”

Section: Full-system Case Studymentioning

confidence: 99%

An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication

Kurth¹,

Rönninger²,

Benz³

et al. 2021

IEEE Trans. Comput.

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On-chip communication infrastructure is a central component of modern systems-on-chip (SoCs), and it continues to gain importance as the number of cores, the heterogeneity of components, and the on-chip and off-chip bandwidth continue to grow. Decades of research on on-chip networks enabled cache-coherent shared-memory multiprocessors. However, communication fabrics that meet the needs of heterogeneous many-cores and accelerator-rich SoCs, which are not, or only partially, coherent, are a much less mature research area. In this work, we present a modular, topology-agnostic, high-performance on-chip communication platform. The platform includes components to build and link subnetworks with customizable bandwidth and concurrency properties and adheres to a state-of-the-art, industry-standard protocol. We discuss microarchitectural trade-offs and timing/area characteristics of our modules and show that they can be composed to build high-bandwidth (e.g., 2.5 GHz and 1024 bit data width) end-to-end on-chip communication fabrics (not only network switches but also DMA engines and memory controllers) with high degrees of concurrency. We design and implement a state-of-the-art ML training accelerator, where our communication fabric scales to 1024 cores on a die, providing 32 TB/s cross-sectional bandwidth at only 24 ns round-trip latency between any two cores.

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Section: Full-system Case Studymentioning

confidence: 99%

An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication

Kurth¹,

Rönninger²,

Benz³

et al. 2021

IEEE Trans. Comput.

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“…We conduct another case study to show how complex specialized hardware such as a GPUscale accelerator [ZSB21] can be extended to support composite enclaves. The accelerator is a 4096-core RISC-V platform that has comparable performance to current machine learning accelerators.…”

Section: Acceleratormentioning

confidence: 99%

“…We perform an extensive security analysis of our prototype, analyzing the implications of our design with respect to side-channels, the unit enclave's interactions with peripherals, their life-cycles, and attestation. We further evaluate two case studies: first, we demonstrate an end-to-end prototype on an FPGA with simple peripherals emulated on a microcontroller; and second, we take an existing accelerator [ZSB21] and integrate it into a composite enclave, adding support for multi-tenant isolation. In the first case study, we developed a prototype on top of an FPGA that is running a RISC-V core with keystone.…”

Section: Introductionmentioning

confidence: 99%

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Composite Enclaves: Towards Disaggregated Trusted Execution

Schneider

Dhar²,

Puddu

et al. 2021

TCHES

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The ever-rising computation demand is forcing the move from the CPU to heterogeneous specialized hardware, which is readily available across modern datacenters through disaggregated infrastructure. On the other hand, trusted execution environments (TEEs), one of the most promising recent developments in hardware security, can only protect code confined in the CPU, limiting TEEs’ potential and applicability to a handful of applications. We observe that the TEEs’ hardware trusted computing base (TCB) is fixed at design time, which in practice leads to using untrusted software to employ peripherals in TEEs. Based on this observation, we propose composite enclaves with a configurable hardware and software TCB, allowing enclaves access to multiple computing and IO resources. Finally, we present two case studies of composite enclaves: i) an FPGA platform based on RISC-V Keystone connected to emulated peripherals and sensors, and ii) a large-scale accelerator. These case studies showcase a flexible but small TCB (2.5 KLoC for IO peripherals and drivers), with a low-performance overhead (only around 220 additional cycles for a context switch), thus demonstrating the feasibility of our approach and showing that it can work with a wide range of specialized hardware.

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“…Indeed, pursuing the maximum bandwidth has been the key metric driving link design, and state-of-the-art links achieve tens or even hundreds of Gbps for high-performance applications [23]- [25]. In domains like the HPC, serial interfaces have already become an essential building block [11]. Short-range serial links can also be used for chiplet-to-chiplet communication [9].…”

Section: Introductionmentioning

confidence: 99%

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

Okuhara

Elnaqib

Dazzi

et al. 2021

IEEE Trans. VLSI Syst.

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The increasing complexity of Internet-of-Things (IoT) applications and near-sensor processing algorithms is pushing the computational power of low-power, battery-operated endnode systems. This trend also reveals growing demands for highspeed and energy-efficient inter-chip communications to manage the increasing amount of data coming from off-chip sensors and memories. While traditional micro-controller interfaces such as SPIs cannot cope with tight energy and large bandwidth requirements, low-voltage swing transceivers can tackle this challenge thanks to their capability to achieve several Gbps of the communication speed at milliwatt power levels. However, recent research on high-speed serial links focused on high-performance systems, with a power consumption significantly larger than the one of low-power IoT end-nodes, or on stand-alone designs not integrated at a system level. This paper presents a low-swing transceiver for the energy-efficient and low power chip-to-chip communication fully integrated within an IoT end-node Systemon-Chip, fabricated in CMOS 65nm technology. The transceiver can be easily controlled via a software interface; thus, we can consider realistic scenarios for the data communication, which cannot be assessed in stand-alone prototypes. Chip measurements show that the transceiver achieves 8.46x higher energy efficiency at 15.9x higher performance than a traditional microcontroller interface such as a single-SPI.

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Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing

Cited by 39 publications

References 8 publications

An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication

An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication

Composite Enclaves: Towards Disaggregated Trusted Execution

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

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