2016
DOI: 10.1587/transele.e99.c.710
|View full text |Cite
|
Sign up to set email alerts
|

Majority Gate-Based Feedback Latches for Adiabatic Quantum Flux Parametron Logic

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
4
0

Year Published

2017
2017
2021
2021

Publication Types

Select...
3
1
1

Relationship

3
2

Authors

Journals

citations
Cited by 10 publications
(4 citation statements)
references
References 17 publications
0
4
0
Order By: Relevance
“…In previous studies [16,18,19], we operated AQFP circuits in a three-phase excitation mode using three ac current sources, in which excitation currents are provided with a phase separation of 120°. In this study, we design new AQFP logic cells so that they can operate in a four-phase excitation mode with a fewer number of ac current sources for high-frequency and low-latency implementation.…”
Section: Four-phase Excitation Schemementioning
confidence: 99%
See 1 more Smart Citation
“…In previous studies [16,18,19], we operated AQFP circuits in a three-phase excitation mode using three ac current sources, in which excitation currents are provided with a phase separation of 120°. In this study, we design new AQFP logic cells so that they can operate in a four-phase excitation mode with a fewer number of ac current sources for high-frequency and low-latency implementation.…”
Section: Four-phase Excitation Schemementioning
confidence: 99%
“…In a previous study [16], we built an AQFP cell library using the 2.5 kA cm −2 Nb standard process (STP2) [17] provided by National Institute of Advanced Industrial Science and Technology (AIST). Using this cell library, we designed and demonstrated several AQFP logic circuits, including an 8 bit CLA [16], a feedback latch [18], and a 21k-junction circuit [19], which is the largest AQFP circuit ever fabricated using STP2.…”
Section: Introductionmentioning
confidence: 99%
“…Memory structures are needed for the IDI and RFX stages of MANA. We created an adiabatic latch by connecting AQFP logic gates in a short four-phase feedback loop similar to the academic latches composed of NAND or NOR gates [33]. This gate-level implementation of an AQFP latch has an enable input which is asserted on the same clock phase as the input data when we want to write into the latch.…”
Section: Memorymentioning
confidence: 99%
“…However, for the generous use of the advantage of the AQFP circuits, reduction of the energy consumption of the memories is essential. Although flip-flops based on AQFP circuits have been proposed in previous study [15][16][17], their circuit area is not small enough for making high-density large-scale memories. Any RAMs for large-scale memories compatible with AQFP circuits have not been realized yet.…”
Section: Introductionmentioning
confidence: 99%