Major Computer Science Challenges At Exascale

Geist, Al; Lucas, Robert F.

doi:10.1177/1094342009347445

Cited by 51 publications

(34 citation statements)

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“…1 For comparison, the original code has 358 lines, whereas our improved version has 982 (without counting the I/O wrappers and the code related to access tables, which is explained later).…”

Section: Before Discovery After Discovery After Updatementioning

confidence: 99%

“…When Omnisc'IO predicts several possible next symbols, they are weighed as 1 # predicted symbols . For instance, if Omnisc'IO predicts that the next symbol will be either a or b and the real next symbol is b, then this prediction is weighed 1 2 . For CM1 and GTC, which run for long periods of time, we show only several iterations starting from the beginning of the run.…”

Section: B Context Predictionmentioning

confidence: 99%

“…This weakness of the I/O system relative to computing capabilities is part of a trend that is worsening as we develop ever more capable computing platforms, and we expect the next generation of systems to have an even larger gap [1]. Moreover, most HPC applications exhibit a periodic behavior, alternating between computation, communication, and I/O phases.…”

Section: Introductionmentioning

confidence: 99%

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Omnisc'IO: A Grammar-Based Approach to Spatial and Temporal I/O Patterns Prediction

Dorier

Ibrahim²,

Antoniu³

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

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Abstract-The increasing gap between the computation performance of post-petascale machines and the performance of their I/O subsystem has motivated many I/O optimizations including prefetching, caching, and scheduling techniques. In order to further improve these techniques, modeling and predicting spatial and temporal I/O patterns of HPC applications as they run has became crucial.In this paper we present Omnisc'IO, an approach that builds a grammar-based model of the I/O behavior of HPC applications and uses it to predict when future I/O operations will occur, and where and how much data will be accessed. Omnisc'IO is transparently integrated into the POSIX and MPI I/O stacks and does not require any modification in applications or higherlevel I/O libraries. It works without any prior knowledge of the application and converges to accurate predictions within a couple of iterations only. Its implementation is efficient in both computation time and memory footprint.

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Section: Before Discovery After Discovery After Updatementioning

confidence: 99%

Section: B Context Predictionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Omnisc'IO: A Grammar-Based Approach to Spatial and Temporal I/O Patterns Prediction

Dorier

Ibrahim²,

Antoniu³

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

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“…This suite is composed of several performance tests that are required to examine the performance and classify the HPC architectures, languages, and libraries [6]: (i) High-Performance Linpack for evaluating the floating point rate of execution for solving a linear system of equations; (ii) Double precision GEneral Matrix Multiply for measuring the floating point rate of execution of double precision real matrix-matrix multiplication; (iii) STREAM for sustainable memory bandwidth evaluation; (iv) PTRANS for testing the total communications capacity of the network; (v) Random Access, which is required for measuring the rate of integer random updates of memory; (vi) Fast Fourier Transform for evaluating the floating point rate of execution of double precision complex one-dimensional Discrete Fourier Transform; and (vii) b-eff for measuring latency and bandwidth of a number of simultaneous communication patterns.…”

Section: High Performance Computing Benchmarks and Evaluation Toolsmentioning

confidence: 99%

“…At the same time, several challenges have been recently identified in order to create large-scale computing systems that meet current and projected application requirements. Most of them are related to system architectures, algorithms, big data processing, and programming models [6]. However, energy cost, resilience, Central Processing Unit (CPU) access latency and memory transfers are key challenges to address in the era of exascale.…”

mentioning

confidence: 99%

New advances in High Performance Computing and simulation: parallel and distributed systems, algorithms, and applications

Smari

Bakhouya

Fiore

et al. 2016

Concurrency and Computation

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INTRODUCTIONRecent developments in research and technological studies have shown that High Performance Computing (HPC) will indeed lead to advances in several areas of Science, engineering, and technology, permitting the successful completion of more computationally intensive and dataintensive problems such as those in healthcare, biomedical and biosciences, climate and environmental changes, multimedia processing, design and manufacturing of advanced materials, geology, astronomy, chemistry, physics, and even financial systems. However, further research is required for developing computing infrastructures, models to support newly evolving architectures, programming paradigms, tools to simulate and evaluate new approaches and solutions, and programming languages that are appropriate for the new and emerging domains and applications.The development of the HPC infrastructure has been accelerated by the advances in silicon technology, which permitted the design of complex systems able to incorporate many hardware and software blocks and cores. More precisely, recent rapid advances in technology and design tools enabled engineers to design systems with hundreds of cores, called multi-processor system-on-chip. These systems are composed of several processing elements, that is, dedicated hardware and software components that are interconnected by an on-chip interconnect. According to Moore's law, the number of cores on-chip will double every 18 months; therefore, thousands of cores-on-chip will be integrated in the next 20 years to meet the power and performance requirements of applications.Moreover, current trends on the road to exascale are moving toward the integration of more and more cores into a single chip [1,2]. For example, accelerators and heterogeneous processing offer some opportunities to greatly increase computational performance and to match increasing application requirements [3]. Engineering these computing systems is one of the most dynamic fields in modern Science and technology. That said, there will continue to be a growing demand for more powerful HPC in the upcoming years, not just to tackle basic mounting computing needs but also to lay out the foundations for the HPC market that is becoming potentially larger than the desktop/laptop computer market. Furthermore, HPC is turning out to be a major source of hope for future applications development that require greater amounts of computing resources in various modern Science domains such as bioengineering, nanotechnology, and energy where HPC capabilities are mandatory in order to run simulations and perform visualization tasks.At the time of writing this editorial, petaflop computing is well established [4]. Several architectures are making major breakthroughs: commodity, accelerators on commodity, and special-purpose cores. All of top 500 systems are based on multicore technologies [5]. HPC usage is growing considerably, especially in industry. And significant efforts toward establishing exascale are underway. At the same time, several challenge...

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Voltage Induced Molecular Motors Constitute the Smallest Self‐Assembled Molecular Electronic Counter

Dagar

Bera

Gandi

et al. 2020

Adv Materials Inter

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These transistors occupy limited space in the chip and as predicted by Gordon Moore the size of the transistors have shrunk to the extent that the number of these transistors in the chip has almost doubled roughly in every two years. [6] The shrinking size of the transistor leads to issues such as non-reliable performance of the devices, overheating due to extensive contact resistances, [7,8] and increase of leakage current [9] to name some of them. An alternate method to circumvent the problems is to follow the slow but efficient natural computing method, which is being followed by all the living organisms. The benefit is that the scale of computation is massive, but it is impossible to achieve this with the traditional methods. One of the closest approaches to the natural computing process is to use synthetic molecules which are primarily consisting of carbon atoms and replicate the physical phenomena by using a self-assembled structure where the molecules will be allowed to interact with each other till they reach the minimum energy configuration. Some of the well-known molecules which can be potentially used for this purpose are 2,3,5,6-Tetramethyl-1,4-benzoquinone (DRQ), Rose Bengal, DDQ. The common structural and functional attributes of these molecules are their redox behavior owing to the presence of some redox active groups, [10-12] which alleviate the impossibility of using these molecules for large scale computation. Moreover, these molecules have multiple conformational states [13] with each state having different conductance, which will be useful for assigning different logic states in a group of self-assembled molecules. So, achieving a self-assembled structure for these molecules, one needs the perfect condition for the molecules to come together. Usually, self-assembly is a process to minimize the surface energy of the system. [14] There are multiple reports of achieving selfassembly of organic molecules in a scanning tunneling microscope (STM), [15-21] but the application of these self-assembled structures is limited. [22-24] In a Ultra-High Vacuum (UHV) STM, single molecules have been observed routinely and are manipulated using various techniques. They have been studied as molecular motors by the application of an external stimulus such as electric field, [25,26] optical signal, [27-31] mechanical forces, [32-38] etc. One such exciting process is the change in An electronic counter is an integral component in an analog to digital (A/D) or digital to analog signal conversion circuit. The number of flip-flops (n) in these devices decides the quality of the conversion as the output is proportional to 2 n. Since each flip-flop is a combination of transistors, and each transistor occupies some space, there is a limitation in the quality of conversion. The smallest 4-bit asynchronous counter is built by using a self-assembled redox-active organic molecule 2,3-Dichloro-5,6-dicyano-1,4-benzoquinone (DDQ), where each DDQ molecule is acting as an individual flip-flop which is the building block of a coun...

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Major Computer Science Challenges At Exascale

Cited by 51 publications

References 0 publications

Omnisc'IO: A Grammar-Based Approach to Spatial and Temporal I/O Patterns Prediction

Omnisc'IO: A Grammar-Based Approach to Spatial and Temporal I/O Patterns Prediction

New advances in High Performance Computing and simulation: parallel and distributed systems, algorithms, and applications

Voltage Induced Molecular Motors Constitute the Smallest Self‐Assembled Molecular Electronic Counter

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