Magnetoelastic Clock System for Nanomagnet Logic

Vacca, Marco; Graziano, Mariagrazia; Crescenzo, L. Di; Chiolerio, Alessandro; Lamberti, Andrea; Balma, D.; Canavese, Giancarlo; Celegato, Federica; Enrico, Emanuele; Tiberto, P.; Boarino, Luca; Zamboni, Maurizio

doi:10.1109/tnano.2014.2333657

Cited by 36 publications

(31 citation statements)

References 36 publications

(46 reference statements)

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“…The generated electric field induces a strain in the piezoelectric substrate that in turn causes a mechanical deformation of magnets, making the magnetization vector rotate toward the short side of the magnet. This clock mechanism leads to the lowest possible power consumption, as we demonstrated in [8]. The idea that we propose in this paper is an evolution of that work, and it is described in Section 3.…”

Section: Magneto-elastic Clockmentioning

confidence: 96%

“…Different physical implementations of this technology have been studied in recent years [11]. Among them, the most relevant are: in-plane NML (iNML), magneto-tunnel-junctions (MTJs), perpendicular NML (pNML), and piezo-NML [8,12]. For all these variants, the basic rules remain the same: cells are disposed on one or more planes, designing a specific logic function by interacting among themselves.…”

Section: Nml Implementations and Backgroundmentioning

confidence: 99%

“…In the STT case, metal lines must be connected to the top and bottom of the MTJ [15] in order to drive a current through each MTJ. The same structure can be used for the magneto-elastic clock, but the energy consumption in this case is far lower [8], therefore leading to high-speed, low-power NML circuits.…”

Section: Proposed Structure For Independent Control Of Piezo-nml Devicesmentioning

confidence: 99%

“…The idea is based on the experimental work presented in [7], where a magnet's magnetization is altered through a mechanical stress which is the consequence of the magneto-elastic effect. It represents an evolution of the idea that we originally proposed in [8], but the physical structure of the clock system is different as it permits each magnet to be controlled independently. It allows the operating frequency of NML circuits to be greatly increased, simultaneously reducing the influence of thermal noise.…”

Section: Introductionmentioning

confidence: 99%

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Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

Turvani

D’Alessandro

Vacca

2018

JLPEA

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Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level.

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Section: Magneto-elastic Clockmentioning

confidence: 96%

Section: Nml Implementations and Backgroundmentioning

confidence: 99%

Section: Proposed Structure For Independent Control Of Piezo-nml Devicesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

Turvani

D’Alessandro

Vacca

2018

JLPEA

Self Cite

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“…It is therefore important to design architectures that limit interconnection wires length. For the NML implementation we choose the Magnetoelastic NML [10], which is the NML subtype with the lowest power consumption. The working principle of this technology is outlined in Fig.…”

Section: Nanomagnet Logicmentioning

confidence: 99%

Logic-in-Memory architecture made real

Pala

Causapruno

Vacca

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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The current trend for intensive computational architectures is to adopt massive parallelism, with several concurrent tasks performed simultaneously, as done for example in GPUs. This approach has many advantages, such as the reduced design time given by circuit replication and an increasing in computational speed without the need of higher frequency. It has however evidenced an important bottleneck in data exchange between memory and processor.We envisage a revolutionary path for the future relation between memory and logic in parallel processors, where a new type of architecture exploits the principle of caching to the limit. Our Logic-in-Memory (LIM) architecture mixes logic and memory in the same device, removing the bottleneck of other existing parallel solutions. The architecture we propose, here in its preliminary version, has an array organization and each element in the array is based on three blocks: a logic unit for processing, a smart memory block and a routing structure for inter block communication. In this article we show the benefits of this approach with an application example in the image processing field. We can achieve a 4X computational time reduction for an image processing algorithm (Summed Area Table) with respect to the best architecture present in the literature, even with a preliminary and not optimized version.Besides the adoption of massive parallelism to increase performance, new technologies to open the post-CMOS era are explored. Among them NanoMagnet Logic (NML) is particularly interesting for its ability to mix logic and memory in the same device. We present here the preliminary results of the NML implementation of the LIM architecture. We thus demonstrate that it is not only a good solution for a standard CMOS technology but can also exploit the potential of an emerging technology as NML.

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Efficient and reliable fault analysis methodology for nanomagnetic circuits

Turvani

Riente

Cairo

et al. 2016

Circuit Theory & Apps

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Summary The increasing issues in scaled Complementary Metal Oxide Semiconductor (CMOS) circuit fabrication favor the flourishing of emerging technologies. Because of their limited sizes, both CMOS and emerging technologies are particularly sensitive to defects that arise during the fabrication process. Their impact is not easy to analyze in order to take the necessary countermeasures, especially in the case of circuits of realistic complexity based on emerging technologies. In this work, we propose a new methodology supported by an efficient and reliable tool for the identification of the impact of faults in complex circuits implemented using the emerging technology we are focusing on in this case: nanomagnetic logic. The methodology is based on three main steps: (i) we performed exhaustive physical‐level simulations of basic blocks based on a detailed finite‐element tool in order to have a full characterization, to know their properties in presence of defects, and to have a solid reference point for the following steps; (ii) we developed a model (fanomag) for the basic block behavior suitable for simulations in presence of defects of complex circuits, that is, lighter than a physical level one, but accurate enough to capture the most important features to be inherited at circuit level; (iii) starting from a physical design of complex circuits that we perform using a specific design tool we developed, that is, ToPoliNano, we simulated using fanomag, now embedded in our ToPoliNano tool, the behavior of circuits in presence of multiple sets of fabrication defects using a Monte Carlo approach now included in ToPoliNano as a new feature. In this paper, a specific type of defect is considered as a case study. The framework and methodology are conceived to be easily extended to handle other types of defects and problems due to working conditions that a designer and/or a technologist might want to focus on. The major outcome is then a powerful methodology and tool capable to analyze with a good accuracy nanomagnetic logic complex circuits and architectures both in ideal conditions and in presence of defects with remarkable performance in terms of simulation times. Copyright © 2016 John Wiley & Sons, Ltd.

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Magnetoelastic Clock System for Nanomagnet Logic

Cited by 36 publications

References 36 publications

Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

Logic-in-Memory architecture made real

Efficient and reliable fault analysis methodology for nanomagnetic circuits

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