Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning

Srinivasan, Gopalakrishnan; Sengupta, Abhronil; Roy, Kaushik

doi:10.1038/srep29545

Cited by 181 publications

(164 citation statements)

References 30 publications

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“…In such scenarios, device-level non-idealities are usually treated as a disadvantage. More recently, stochasticity inherent in such devices (for instance, probabilistic switching in presence of thermal noise) have been exploited for computing to implement stochastic versions of their deterministic counterparts [33], [34]. Due to additional information encoding capacity in the switching probability, such devices can be scaled down to single bit instead of multi-bit representations.…”

Section: Discussionmentioning

confidence: 99%

All-Spin Bayesian Neural Networks

Yang

Malhotra

et al. 2020

IEEE Trans. Electron Devices

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Probabilistic machine learning enabled by the Bayesian formulation has recently gained significant attention in the domain of automated reasoning and decision-making. While impressive strides have been made recently to scale up the performance of deep Bayesian neural networks, they have been primarily standalone software efforts without any regard to the underlying hardware implementation. In this paper, we propose an "All-Spin" Bayesian Neural Network where the underlying spintronic hardware provides a better match to the Bayesian computing models. To the best of our knowledge, this is the first exploration of a Bayesian neural hardware accelerator enabled by emerging post-CMOS technologies. We develop an experimentally calibrated device-circuit-algorithm co-simulation framework and demonstrate 24× reduction in energy consumption against an iso-network CMOS baseline implementation.

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Section: Discussionmentioning

confidence: 99%

All-Spin Bayesian Neural Networks

Yang

Malhotra

et al. 2020

IEEE Trans. Electron Devices

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“…They can currently be fabricated down to a 10 nm length scale [9,10]. netic tunnel junctions that can switch stochastically in the presence of current pulses [23,24].…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Stochastic Computing with Superparamagnetic Tunnel Junctions

et al. 2020

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Superparamagnetic tunnel junctions have emerged as a competitive, realistic nanotechnology to support novel forms of stochastic computation in CMOS-compatible platforms. One of their applications is to generate random bitstreams suitable for use in stochastic computing implementations. We describe a method for digitally programmable bitstream generation based on pre-charge sense amplifiers which is more energy efficient than previously explored alternatives. The energy savings offered by this digital generator survive when we use them as the fundamental units of a neural network architecture. To take advantage of the potential savings, we codesign the algorithm with the circuit, rather than directly transcribing a classical neural network into hardware. The flexibility of the neural network mathematics compensates for explicitly energy efficient choices we make at the device level. The result is a convolutional neural network design operating at ≈ 150 nJ per inference with 97 % performance on MNIST-nearly an order of magnitude more energy efficiency than comparable proposals in the recent literature. * matthew.daniels@nist.gov † mark.stiles@nist.govThe low energy, truly random behavior, ease of control, and established compatibility with complementarymetal-oxide-semiconductor (CMOS) circuitry has led to the use of SMTJs as the basis for a number of novel computing schemes [11][12][13]. SMTJs were proposed to implement the concept of probabilistic bits, or "p-bits," which were leveraged for applications as Bayesian neural networks [14][15][16], invertible Boolean logic [17,18], reservoir computing [19], and Ising network models applied to optimization problems [20,21]. SMTJs were also proposed as stochastic neural units [22] that can interact with synaptic units, emulated by crossbar arrays of mag-

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“…Figure 31 shows the input and output of an integrate-and-fire neuron with memristor synapses taking into account the stochastic behavior of the memristor. Recently, a heterostructure composed of a MTJ and a heavy metal as a stochastic binary synapse was proposed [80]. Synaptic plasticity was achieved by the stochastic switching of the MTJ conductance states, based on the temporal correlation between the spiking activities of the interconnecting neurons.…”

Section: Bio-inspired Ultra-low-power Computingmentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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Abstract:In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

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Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning

Cited by 181 publications

References 30 publications

All-Spin Bayesian Neural Networks

All-Spin Bayesian Neural Networks

Energy-Efficient Stochastic Computing with Superparamagnetic Tunnel Junctions

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

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