MAGIC—Memristor-Aided Logic

Kvatinsky, Shahar; Белоусов, Д. Р.; Liman, Slavik; Satat, Guy; Wald, Nimrod; Friedman, Eby G.; Kolodny, Avinoam; Weiser, Uri

doi:10.1109/tcsii.2014.2357292

Cited by 646 publications

(410 citation statements)

References 19 publications

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“…It is a parallel-processing, functionally complete logic design scheme, unlike some published sequential processing approaches, such as the CMOS-like [14], MAGIC [17], and IMPLY [19] logics. It enables the parallel execution of single-step digital logic operations, exploiting the threshold-dependent switching behavior of memristors and of their simple series connection.…”

Section: B Basics Of Reram-based Logic Circuitsmentioning

confidence: 99%

“…For instance, if we first apply either "10" or "01" and then, immediately after, "00," then due to the nonvolatility of the memristors, the final result will not be correct. Consequently, it is necessary to initialize every gate via a reset pulse in between each input logic combination, a requirement common to several memristive logic design approaches [17], [19]. To this end, initialization drivers access the RL and LIL/LOL and are assumed to be distributed around the computing-array.…”

Section: B Basics Of Reram-based Logic Circuitsmentioning

confidence: 99%

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Crossbar-Based Memristive Logic-in-Memory Architecture

Papandroulidakis

Vourkas

Abusleme

et al. 2017

IEEE Trans. Nanotechnology

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Aquesta és una còpia de la versió draft d'un article publicat a IEEE transactions on nanotechnologyhttp://hdl.handle.net/2117/104473 Papandroulikadis, G., Vourkas, I., Abustelema, A., Sirakoulis, G., Rubio, A. Crossbar-based memristive logic-in-memory architecture. "IEEE transactions on nanotechnology", 1 Abril 2017, vol. 16, núm. 3, p. 491-501. DOI: 10.1109/TNANO.2017 © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1Abstract-The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We present an analysis of circuit resources, integration density, and logic computation parallelism and prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder (HA) and sum-of-products logic functions.

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Section: B Basics Of Reram-based Logic Circuitsmentioning

confidence: 99%

Section: B Basics Of Reram-based Logic Circuitsmentioning

confidence: 99%

Crossbar-Based Memristive Logic-in-Memory Architecture

Papandroulidakis

Vourkas

Abusleme

et al. 2017

IEEE Trans. Nanotechnology

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“…So far a variety of approaches has been proposed for synthesis of logic-in-memory computing circuits, mostly based on material implication (IMP: p → q =p ∨ q) [12], [13] and some using other basic operations [14], [15], [11]. In all these approaches, the target function can only be executed using a certain number of RRAM devices and after a number of operations, which increases rapidly as the size of the function increases.…”

Section: Logic-in-memory Write Trafficmentioning

confidence: 99%

Endurance management for resistive Logic-In-Memory computing architectures

Shirinzadeh

Soeken

Gaillardon

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low write endurance. In this paper, we focus on balancing memory write traffic as a solution to extend the lifetime of resistive crossbar architectures. As a case study, we monitor the write traffic in a Programmable Logic-in-Memory (PLiM) architecture, and propose an endurance management scheme for it. The proposed endurance-aware compilation is capable of handling different trade-offs between write balance, latency, and area of the resulting PLiM implementations. Experimental evaluations on a set of benchmarks including large arithmetic and control functions show that the standard deviation of writes can be reduced by 86.65% on average compared to a naive compiler, while the average number of instructions and RRAM devices also decreases by 36.45% and 13.67%, respectively.

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“…This technology exists in research centers and presents issues in terms of excessive area, though it appears more promising in terms of computational power, co-integrating memory and computing. Currently available studies have been conducted along the lines of nanoelectronics, logic, [142], modeling and memory [143].…”

Section: Device Level the Memristor And Crossbar Realizationsmentioning

confidence: 99%

Neuromorphic microelectronics from devices to hardware systems and applications

Schmid

2016

NOLTA

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Neuromorphic systems aiming at mimicking some characteristics of the nervous systems of living humans or animals have been developed since the late 1980s', taking benefit of intrinsic properties and increasing performances of the successive silicon fabrication technologies. A regain of interest has been observed in the middle of the 2010s', which manifests itself from the emergence of large-scale projects integrating various computational and hardware perspectives, by the increased interest and involvement of industry and the growth of the volume of scientific publications. This paper reviews research directions and methods of neuromorphic microelectronics hardware, the developed hardware and its performance, and discusses current issues and potential future developments.

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MAGIC—Memristor-Aided Logic

Cited by 646 publications

References 19 publications

Crossbar-Based Memristive Logic-in-Memory Architecture

Crossbar-Based Memristive Logic-in-Memory Architecture

Endurance management for resistive Logic-In-Memory computing architectures

Neuromorphic microelectronics from devices to hardware systems and applications

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