Macro-models for high-level area and power estimation on FPGAs

Abstract

As more and more complex applications are implemented on FPGAs, high-level design tools are needed to reduce the design time. A good high-level synthesis tool usually has an automated design space exploration pass to determine the effects of various compiler optimizations on the area and power of the synthesized hardware. Such a pass needs early estimation of area and power. Towards this end, we have developed high-level equation based area and power macro-models for various RTL level operators such as adders, multipliers, and logical operators. The area model is parameterized with the bit width of the device and the power model takes into account input switching activity and input spatial correlation as well as input bit width. These models are derived by actual synthesis of these RTL operators using back-end logic synthesis and place-and-route tools. Compared with the other approaches, our method generated a uniform macro-model for each operator with fewer coefficients and sometimes lower degrees. It is also easier to analyze the power sensitivity to different parameters. Experimental results show that these area and power models are accurate and efficient.

Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators

“…To speed up design exploration, we propose an approach similar to [3], [7], where the large design space is sampled and then regression analysis and statistical inference are used to create mathematical models that estimate the target metrics over the entire design space. These sample combinations are implemented in the design and the resultant metrics characterized from real measurements (e.g., power) and/or from synthesis tool results (e.g., area).…”

“…The relationship between architectural parameters and the speed of FPGA implementations are explored in [2]. Jiang et al use a least squares regression analysis to estimate the power and area consumptions of specific computation units of an implementation [3]. Their work is similar to the work done by Lee et al in the computer architecture domain with regression based models for microarchitectural design space exploration [4].…”

An Automatic Power Estimation Methodology for FPGA-Based Digital Signal Processing Systems

“…Macro modules-based estimation techniques are introduced at the gate level and operation level [7][8][9]. They aim to build an IP library and obtain some signal activity probabilities through extensive simulations.…”

Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme

“…and operation level (MUL, MUX, etc. ), macro modules-based estimation techniques are presented [13][14][15]. They aim to build an IP library and depend on obtaining some signal activity probabilities through simulation.…”

“…The results of previous research efforts [8][9][10][11][12][13][14][15] encouraged FPGA vendors to provide power estimators within their commercial platforms [16][17]. The estimators work on post place-and-route (P&R) stage, so they provide accurate results, but the problem is the long time needed to reach such stage.…”