Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators

Abstract

The reconfigurability of Field Programmable Gate Arrays (FPGAs) makes them an attractive platform for accelerating algorithms. Accelerating a particular algorithm is a challenging task as the large number of possible algorithmic and hardware design parameters lead to different accelerator variant implementations, each with its own metrics such as performance, area, power, and arithmetic accuracy characteristics. To identify these parameters that optimize the accelerator for certain metrics, we propose techniques for fast design space exploration and non-linear multi-objective optimization (e.g., minimize power under arithmetic inaccuracy bounds). Our methodology samples a small part of the design space and uses measurements from the sampled implementations to train mathematical models for the different metrics. To automate and improve the model generation process, we propose the use of L1-regularized least squares regression techniques. To demonstrate the effectiveness of our approach, we implement a high-throughput real-time accelerator for image debluring. We demonstrate the accuracy (e.g., within 8% for power modeling) of our modeling techniques and their ability to identify the optimal accelerator designs with large speed-ups (340×) in comparison to brute-force enumeration.

Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators

“…Dedicated ASICs remove the slow and generic architectural limitations of software-based systems. ASSPs exploit the parallelism and efficiencies of the digital signal processors (DSPs) and hardwired application-specific accelerators, usually managed by a standard controller core like ARM, or PowerPC [Rossi et al 2013]. Similarly, FPGAs are ideal for inexpensive prototyping platforms to implement high-throughput solutions.…”