Machine Learning-Based Edge Placement Error Analysis and Optimization: A Systematic Review

Ngo, Anh T.; Dey, Bappaditya; Halder, Sandip; Gendt, Stefan De; Wang, Changhai

doi:10.1109/tsm.2022.3217326

Cited by 4 publications

(5 citation statements)

References 67 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…With the evolution of Moore's Law, the feature of the semiconductor device continues to shrink [1]. It is essential to reduce the edge placement error (EPE) to maintain the performance and high yield of a device [2,3]. EPE serves as a metric for quantifying the fidelity of lithography technology and the EPE budget decreases with the iteration of the logic node [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

“…In particular, for the most advanced node (e.g., EUV lithography), typically, EPE is dominated by stochastics (>50%) [3,8]. In contrast, the overlay consumption decreases from 34% (for 9~13 nm logic nodes) to 21% (for 5~7 nm logic nodes) of the EPE budget [2,6]. Therefore, the improvement of overlay performance is an efficient approach to reducing EPE.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Mitigating the Impact of Asymmetric Deformation on Advanced Metrology for Photolithography

Yang,

Yao,

Cao

et al. 2024

Applied Sciences

View full text Add to dashboard Cite

Controlling overlay in lithography is crucial for improving the yield of integrated circuit manufacturing. The process disturbances can cause undesirable morphology changes of overlay targets (such as asymmetric grating), which can significantly impact the accuracy of overlay metrology. It is essential to decouple the overlay target asymmetry from the wafer deformation, ensuring that the overlay metrology is free from the influence of process-induced asymmetry (e.g., grating asymmetry and grating imbalance). Herein, we use an asymmetric grating as a model and show that using high-diffraction-order light can mitigate the impact of asymmetric grating through the rigorous coupled-wave analysis (RCWA) method. In addition, we demonstrate the diffraction efficiency as a function of the diffraction order, wavelength, and pitch, which has guiding significance for improving the measurement accuracy of diffraction-based overlay (DBO) metrology.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Mitigating the Impact of Asymmetric Deformation on Advanced Metrology for Photolithography

Yang,

Yao,

Cao

et al. 2024

Applied Sciences

View full text Add to dashboard Cite

show abstract

“…Since the advanced technological node becomes widely adopted in current IC manufacture, the metrology and process control as well as the resolution enhancement technology play much more critical role nowadays than before. As the prerequisite of the further process analysis such as EPE 1 (Edge Placement Error) and CDU [2][3][4] (Critical Dimension Uniformity), the contour abstraction of SEM (Scan Electron Microscopy) image should be well done. This involves a detailed process flow including the placement of anchor points, the record of the SEM image according to proper settings, the preprocessing of the SEM images including the distortion correction, denoising and the choose of the ROI (region of interest) for image analysis.…”

Section: Introductionmentioning

confidence: 99%

SEM image contour extraction with deep learning method

Gu,

Shang,

et al. 2023

Photomask Technology 2023

View full text Add to dashboard Cite

“…Machine learning solutions have become an attractive tool for future process control and monitoring purposes [4]. A systematic survey was conducted on recent research works, which demonstrates different machine learning/deep learning techniques applied towards improving EPE in semiconductor manufacturing domain [5]. The methodology deployed in this study involves using the overlay metrology data from early process steps.…”

Section: Introductionmentioning

confidence: 99%

SEM image denoising with unsupervised machine learning for better defect inspection and metrology

Dey

Halder

Khalil

et al. 2021

Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV

View full text Add to dashboard Cite

Moore's Law states that transistor density will double every two years, which is sustained until today due to continuous multidirectional innovations (such as extreme ultraviolet lithography, novel patterning techniques etc.), leading the semiconductor industry towards 3 nm node (N3) and beyond. For any patterning scheme, the most important metric to evaluate the quality of printed patterns is edge placement error, with overlay being its largest contribution. Overlay errors can lead to fatal failures of IC devices such as short circuits or broken connections in terms of pattern-to-pattern electrical contacts. Therefore, it is essential to develop effective overlay analysis and control techniques to ensure good functionality of fabricated semiconductor devices. In this work we have used an imec N-14 BEOL process flow using litho-etch-litho-etch (LELE) patterning technique to print metal layers with minimum pitch of 48nm with 193i lithography. Fork-fork structures are decomposed into two mask layers (M1A and M1B) and then the LELE flow is carried out to make the final patterns. Since a single M1 layer is decomposed into two masks, control of overlay between the two masks is critical. The goal of this work is of two-fold as, (1) to quantify the impact of overlay on capacitance and (2) to see if we can predict the final capacitance measurements with selected machine learning models at an early stage. To do so, scatterometry spectra are collected on these electrical test structures at (a) post litho, (b) post TiN hardmask etch, and (c) post Cu plating and CMP. Critical Dimension (CD) and overlay measurements for line/space (L/S) pattern are done with SEM post litho, post etch and post Cu CMP. Various machine learning models are applied to do the capacitance prediction with multiple metrology inputs at different steps of wafer processing. Finally, we demonstrate that by using appropriate machine learning models we are able to do better prediction of electrical results.

show abstract

Machine Learning-Based Edge Placement Error Analysis and Optimization: A Systematic Review

Cited by 4 publications

References 67 publications

Mitigating the Impact of Asymmetric Deformation on Advanced Metrology for Photolithography

Mitigating the Impact of Asymmetric Deformation on Advanced Metrology for Photolithography

SEM image contour extraction with deep learning method

SEM image denoising with unsupervised machine learning for better defect inspection and metrology

Contact Info

Product

Resources

About