Mach-Zehnder silicon modulator on bulk silicon substrate; toward DRAM optical interface

Shin, Dongjae; Lee, K. H.; Ji, Ho-Chul; Na, K. W.; Kim, S. G.; Bok, J. K.; You, Yong-Sang; Kim, S. S.; Joe, In-Sung; Suh, Sungsoo; Pyo, Junghyung; Shin, Yong-hwack; Ha, K. H.; Park, Y. D.; Chung, Chilhee

doi:10.1109/group4.2010.5643376

Cited by 9 publications

(5 citation statements)

References 7 publications

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“…Note that the WG is offset from the BOX center to avoid the coalescence boundary. The details of the SPE can be found in the previous reports [13]- [15]. The process flow to embed the PIC into DRAM is briefed in Fig.…”

Section: Dram Applicationmentioning

confidence: 99%

“…However, the resistance increase and its impact to the device speed have been insignificant as shown in the 25-Gbps lasers, modulators, and photodiodes successfully developed on the BS platform. Details on the Sionly BS devices can be found in the previous reports [13], [14], and this section focuses on the III/V-on-BS devices, which have been recently added to the BS device library after the DRAM integration. The operating wavelength band of the III/V-on-BS devices has been the O band.…”

Section: Performance Of Iii/v-on-bs Platformmentioning

confidence: 99%

See 1 more Smart Citation

Bulk-Si Platform: Born for DRAM, Upgraded With On-Chip Lasers, and Transplanted to LiDAR

Shin

Byun

Shim

et al. 2022

J. Lightwave Technol.

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The CMOS industry has been expecting silicon photonics to provide photonic and electro-photonic integrated circuits based on the CMOS processes and infrastructures for scalability of incumbent technology evolutions and creation of novel technologies. However, the compatibility with the legacy CMOS has been compromised with the development convenience of early silicon photonics in that the specialty silicon-on-insulator substrates have been widely used as integration platforms. Since this specialty substrate may hinder the photonics integration with legacy volume products later, a legacy-friendly integration platform with a generic bulk-silicon substrate has been developed for better compatibility. This paper overviews the bulk-silicon photonics platform born for DRAM integration, upgraded with III/V-on-bulk-Si lasers, and transplanted to LiDAR applications requiring the virtuous cycle of cost and volume. The photonics integration with DRAM was to resolve the speed-capacity tradeoff in the DRAM interconnects, and technical feasibility as well as lessons learned from the integration attempt are reviewed. The bulk-silicon device performance approaches that of silicon-oninsulator devices with the thermal advantage of ~40-% lower thermal impedance and the optical disadvantage of ~0.4-dB/mm higher waveguide loss. In the LiDAR applications, detection performance up to ~20 m at 20 fps by a single-chip scanner integrating tunable laser, semiconductor optical amplifiers, and optical phased array are presented with future outlooks.

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Section: Dram Applicationmentioning

confidence: 99%

Section: Performance Of Iii/v-on-bs Platformmentioning

confidence: 99%

Bulk-Si Platform: Born for DRAM, Upgraded With On-Chip Lasers, and Transplanted to LiDAR

Shin

Byun

Shim

et al. 2022

J. Lightwave Technol.

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“…A basic set of the required photonic devices that must be integrated in the process is shown in Figure 7. Currently, device and process development has focused on either solid phase epitaxy (SPE) silicon waveguides [34,35] or deposited polycrystalline silicon waveguides [3]. Both approaches have yielded waveguide losses below 10 dB/cm.…”

Section: Drammentioning

confidence: 99%

Integration of silicon photonics into electronic processes

2013

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Front-end monolithic integration has enabled photonic devices to be fabricated in bulk and thin-SOI CMOS as well as DRAM electronics processes. Utilizing the CMOS generic process model, integration was accomplished on multi-project wafers that were shared by standard electronic customers without requiring in-foundry process changes. Simple die or wafer-level post-processing has enabled low-loss waveguides by the removal of the substrate within photonic regions. The custom-process model of the DRAM industry instead enabled optimization of the photonic device fabrication process and the potential elimination of post-processing requirements. Integrated singlecrystalline silicon waveguide loss of ~3 dB/cm has been achieved within a 45nm thin-SOI CMOS process that is currently used to manufacture microprocessors [1]. A fully monolithic photonic transmitter including a pseudo-random bit sequence (PRBS) generating digital backend was also demonstrated within this process [1]. The constraints of zero-change integration have limited achieved polysilicon waveguide loss to ~50 dB/cm with commercially available bulk CMOS processes [2]. Custom polysilicon deposition and processing conditions available for DRAM integration have also led to the demonstration of ~6 dB/cm loss waveguides suitable for integration within electronics processes utilizing bulk silicon starting substrates [3]. An overview of required process features, device design guidelines and integration methodology tradeoffs will be presented. Relevant device metrics of area and energy efficiency as well as achievable photonic device performance will be presented within the context of monolithic front-end integration within state-ofthe-art electronics processes. Applications of this research towards the implementation of a computer system utilizing photonic interconnect for core-to-memory communication will also be discussed.

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“…For instance, even though a CMOS SOI platform is of interest to DRAM vendors, they continue to manufacture with bulk Si; given the tiny margins on commodity memories, a transition to SOI DRAM remains unlikely. However, with local oxidation and poly Si recrystallization it would be possible to make SiPhotonics components on bulk Si for eventual co-integration, and thereby produce optically enabled DRAMs [12]. Despite good low-speed modulation devices, the reported metrics still trail the equivalent speed and performance found on SOI.…”

Section: Monolithic Co-integration Versus Hybrid Integrationmentioning

confidence: 99%

Scaling hybrid-integration of silicon photonics in Freescale 130nm to TSMC 40nm-CMOS VLSI drivers for low power communications

Cunningham

Shubin

Thacker

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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We report new developments on hybrid integration that attaches CMOS driver circuits to silicon photonic (SiPhotonic) devices built in Silicon on Insulator (SOI) technology. This low-parasitic hybrid integration approach enables energy efficient links based on aggressive silicon photonic devices and low power, high speed circuits. The silicon photonic components are fabricated in the 130 nm Cu node of Freescale's SOI-CMOS technology while the CMOS driver circuits are fabricated in 40 nm TSMC ELK technology.The two types of chips are using 20 um diameter solder bumps. We further present progress on scaling these solder bumps to 10 micron diameter and below as well as developing a wafer scale microsolder process module.Finally, we report progress integrating hybrids that include SOI chips with a partially removed backside. Under full SOI handler removal this bonding geometry is akin to the extreme limit of wafer thinning used in today's vertical chip stacking (3D) approaches.

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Mach-Zehnder silicon modulator on bulk silicon substrate; toward DRAM optical interface

Cited by 9 publications

References 7 publications

Bulk-Si Platform: Born for DRAM, Upgraded With On-Chip Lasers, and Transplanted to LiDAR

Bulk-Si Platform: Born for DRAM, Upgraded With On-Chip Lasers, and Transplanted to LiDAR

Integration of silicon photonics into electronic processes

Scaling hybrid-integration of silicon photonics in Freescale 130nm to TSMC 40nm-CMOS VLSI drivers for low power communications

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