Scaling hybrid-integration of silicon photonics in Freescale 130nm to TSMC 40nm-CMOS VLSI drivers for low power communications

Abstract

We report new developments on hybrid integration that attaches CMOS driver circuits to silicon photonic (SiPhotonic) devices built in Silicon on Insulator (SOI) technology. This low-parasitic hybrid integration approach enables energy efficient links based on aggressive silicon photonic devices and low power, high speed circuits. The silicon photonic components are fabricated in the 130 nm Cu node of Freescale's SOI-CMOS technology while the CMOS driver circuits are fabricated in 40 nm TSMC ELK technology.The two types of chips are using 20 um diameter solder bumps. We further present progress on scaling these solder bumps to 10 micron diameter and below as well as developing a wafer scale microsolder process module.Finally, we report progress integrating hybrids that include SOI chips with a partially removed backside. Under full SOI handler removal this bonding geometry is akin to the extreme limit of wafer thinning used in today's vertical chip stacking (3D) approaches.

Reconfigurable silicon photonic networks-on-chip

“…The low-power optical devices can also operate in combination with energyefficient CMOS drivers and amplifiers [13]. Hybrid electronicphotonics integration [14] as well as monolithic integration with ICs [15] have been demonstrated.…”

High-efficiency Si optical modulator using Cu travelling-wave electrode

“…IBM reported a 25 Gbps microring modulator using Cu electrode [18] and a 90 nm CMOS-photonics technology node for 25 Gbps transceiver [22] in 2012. Oracle labs reported hybrid-integration of silicon photonics using Cu electrode in 2012 [23]. Luxtera reported a 4 × 25 Gbps transceiver [24].…”