Luo Rudy Phase I excitation modeling towards HDL coder implementation for real-time simulation

Abstract

Abstract-This paper presents the simulation study of nonlinear dynamic of cardiac excitation based on Luo Rudy Phase I (LR-I) model towards numerical solutions of ordinary differential equations (ODEs) responsible for cardiac excitation on field programmable gate arrays (FPGAs). As computational modeling needs vast of simulation time, a realtime hardware implementation using FPGA could be the solution as it provides high configurability and performance. For rapid prototyping, MATLAB Simulink that offers a link with the FPGA has been used. Through Simulink HDL Coder, a tool in the MATLAB software that capable to convert the MATLAB Simulink blocks into hardware description language (HDL) code and an FPGA-in-the-loop (FIL) and co-simulation for verification, FPGA hardware implementation can be done. As a result, the LR-I excitation model is successfully simulated by using the MATLAB Simulink and the VHDL code has been successfully generated by the HDL Coder after fixed-point optimization is done. The FIL verification on actual FPGA board also has shown quantitatively comparable results to the MATLAB Simulink simulation. Therefore, the design flow has given a positive outlook in developing this FPGA stand-alone implementation.

Cardiac excitation modeling: HDL coder optimization towards FPGA stand-alone implementation

“…Firstly, conversion from the continuous-time to a discrete-time modeling must be done and all blocks used in the designed model must be from the HDL supported blocks which known as hdlsupported library. Floating-point data type to fixed-point data type conversion is also needed as stated in the previous works [9,10,11] in which the fixed-point data type will be set using a suitable WL and FL. Here, the WL and FL can be defined as the number of bits in the representation of signals and the scaling or binary point location represents the number of bits of the integer part, respectively.…”

Model-Based Design Optimization using CDFG for Image Processing on FPGA

“…In literature [1], [2], and [3], the authors proposed alternative approaches by using a Model-Based Design (MBD) that is a practical design methodology and able to develop rapid prototyping by using MAT-LAB/Simulink. In literature [4] and [5], the authors proposed optimization, such as xed-point optimiza-tion, to reduce the area consumption for a lower-cost FPGA board with limited resources.…”

“…In literature [4] and [5], the authors proposed optimization, such as xed-point optimiza-tion, to reduce the area consumption for a lower-cost FPGA board with limited resources. Many applications employed only a few conditions without nested loops [1], [2], [3], [4], and [5]. So, this literature cannot be a good candidate for complex models.…”