2014 IEEE International Conference on Control System, Computing and Engineering (ICCSCE 2014) 2014
DOI: 10.1109/iccsce.2014.7072771
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Cardiac excitation modeling: HDL coder optimization towards FPGA stand-alone implementation

Abstract: The aim of this paper is to discuss the optimization of the hardware description language (HDL) design using fixedpoint optimization and speed optimization through a pipelining method. This optimization is very crucial to achieve the best performance in terms of speed, area and power consumption of the generated HDL code before deploying the field programmable gate array (FPGA) stand-alone implementation. As computational mathematical modeling needs immense amounts of simulation time, FPGA could bring the solu… Show more

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Cited by 6 publications
(4 citation statements)
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“…The simulation output of the action potential for cellular excitation on the FPGA Virtex-6 was obtained from the Chipscope Pro. These design processes have been reported in detail in our previous work [26]. Based on the FPGA-on-board simulation, cardiac excitation response to periodic stimulation current trains with different intervals of time (t) and intensity of stimulation current (Isti) were compared to those of the computer simulation.…”
Section: Fpga Rapid Prototyping Design For the Simulation Of The Card...mentioning
confidence: 99%
“…The simulation output of the action potential for cellular excitation on the FPGA Virtex-6 was obtained from the Chipscope Pro. These design processes have been reported in detail in our previous work [26]. Based on the FPGA-on-board simulation, cardiac excitation response to periodic stimulation current trains with different intervals of time (t) and intensity of stimulation current (Isti) were compared to those of the computer simulation.…”
Section: Fpga Rapid Prototyping Design For the Simulation Of The Card...mentioning
confidence: 99%
“…The model-based design generally provides an effective improvement in terms of system reliability and reduces the total project time up to 33% and the cost by 20% compared to the traditional methods (hand-written code) [23]. The floating-point model needs to be converted to fixed point in order to reduce the hardware resources [19]. The steering system was designed and simulated using MATLAB Simulink and implemented on SoC (System on Chip) target using embedded coder and HDL coder.…”
Section: Design Of the Mpc Controller And Hdl Code Generationmentioning
confidence: 99%
“…In literature [1], [2], and [3], the authors proposed alternative approaches by using a Model-Based Design (MBD) that is a practical design methodology and able to develop rapid prototyping by using MAT-LAB/Simulink. In literature [4] and [5], the authors proposed optimization, such as xed-point optimiza-tion, to reduce the area consumption for a lower-cost FPGA board with limited resources. Many applications employed only a few conditions without nested loops [1], [2], [3], [4], and [5].…”
Section: Introductionmentioning
confidence: 99%
“…In literature [4] and [5], the authors proposed optimization, such as xed-point optimiza-tion, to reduce the area consumption for a lower-cost FPGA board with limited resources. Many applications employed only a few conditions without nested loops [1], [2], [3], [4], and [5]. So, this literature cannot be a good candidate for complex models.…”
Section: Introductionmentioning
confidence: 99%