<title>Gold damascene interconnect technology for millimeter-wave photonics on silicon</title>

Abstract

Thick-gold-multilevel damascene-interconnect technology makes it possible to fabricate >10-µm-feature ultrahighspeed devices on Si. Adding H 2 O 2 to a conventional KIO 3 -based slurry triples the removal rate of gold in chemical mechanical polishing (CMP). A ratio of H 2 O 2 to slurry of ~1:1 is found to be the optimum for obtaining the highest gold removal rate. X-ray photoelectron spectroscopy (XPS) analyses show that gold is oxidized in spite of its chemical stability when the removal rate is high. The gold is oxidized due to the reduction of iodine at the optimum H 2 O 2 mixture ratio. This CMP of gold enabled us to make a thick (>10 µm) gold-multilevel damascene-interconnection structure for the first time. Integration of full-wafer wafer-bonded uni-traveling carrier photodiodes (UTC-PDs) with the gold multilevel interconnections as coplanar waveguides (CPWs) on a Si wafer has been achieved using this gold-CMP process.

Planarization optimization of RF-MEMS switches with a gold membrane

“…The most commonly used sacrificial layers are photoresist and polyimide because of low roughness and high thermal creeping. Moreover chemical mechanical polishing (CMP), mainly used in microelectronics for multilevel metals planarization [8,9], has begun to be used for polymers [10] and MEMS applications [11]. Metal or SiO 2 was investigated because CMP permits us to deal easily with non-flat problems [8], but roughness and thermal stress issues still remain limiting their usage.…”