&lt;title&gt;Framework for identifying recommended rules and DFM scoring model to improve manufacturability of sub-20nm layout design&lt;/title&gt;

Pathak, Piyush; Madhavan, Sriram; Malik, Shobhit; Wang, Lynn T. N.; Capodieci, Luigi

doi:10.1117/12.916288

Cited by 11 publications

(3 citation statements)

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“…sqrt(mean(yactual-ypred) 2 )/(y max actual -y min actual) (3) where yactual is the actual value and ypred is the predicted value. y max actual and y min actual are the actual maximum and minimum values of the entire data set, respectively.…”

Section: Metrics For Evaluating the Quality Of The Machine Learning M...unclassified

Design for manufacturability (DFM) physical verification using machine learning

Wang

Johnsen

Tanev

et al. 2023

DTCO and Computational Patterning II

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Design for Manufacturability (DFM) physical verification checks using supervised Machine Learning (ML) are developed and optimized to identify via-metal enclosure weak points to prevent via opens caused by line-end shortening post-retargeting. Various methods for generating feature vectors and neural network architectures are evaluated for optimizing training time an d ML model quality. Techniques include applying PCA to image-based density vectors generated from layout clips to identify the principle components or using localized layout features directly for model training. Results show that for a sample size of 3 00k vias, the image-based density vectors versus localized layout feature vectors achieve similar correlation coefficients of 0.95 and normalized RMSE of 0.11, with a training time of 10+ hours versus 1+ minute, respectively.

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Section: Metrics For Evaluating the Quality Of The Machine Learning M...unclassified

Design for manufacturability (DFM) physical verification using machine learning

Wang

Johnsen

Tanev

et al. 2023

DTCO and Computational Patterning II

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show abstract

“…Because of these advantages, many scoring methodologies have been proposed and are being used for layout optimization [4] [5]. This paper is based off of the Manufacturability Aware Scoring (MAS) methodology demonstrated in [6].…”

Section: Manufacturabilitymentioning

confidence: 99%

Decomposition-aware layout optimization for 20/14nm standard cells

et al. 2014

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Decomposition-aware layout design improvements for 8, 9, 11, and 13-track 20/14nm standard cells are presented. Using a decomposition-aware scoring methodology that quantifies the manufacturability of layouts, the Double Patterning Technology (DPT)-compliant layouts are optimized for DPT-specific metrics that include: the density difference between the two decomposition mask layers, the enclosure of stitching areas, the density of stitches, and the design regularity of stitching areas. For a 9-track standard cell, eliminating the stitches from the layout design improved the composite score from 0.53 to 0.70.

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“…Manufacturability Analysis and Scoring (MAS) is a well established DFM check that has been introduced for advanced semiconductor technology nodes <=55nm [1,2,3]. The deck analyzes designs for the usage of minimum ground rules.…”

Section: Introductionmentioning

confidence: 99%

Machine learning architecture evaluation for fast and accurate weak point detection

Lee

Schroeder

Rezaeifakhr

et al. 2023

DTCO and Computational Patterning II

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This paper proposes a new methodology that can greatly accelerate Manufacturability Analysis & Scoring (MAS) deck runtime. The intention of this work is to provide a quick preview check to ensure that a new design will pass MAS signoff. Instead of running the deck on the full design, the input design is sampled down to a few random locations which are then analyzed. Furthermore, the actual MAS checks are replaced by an ML trained lookup methodology that keys off very simple design parameter like layer area density and layer perimeter density. The output of the deck is a simple PASS/FAIL statement and a range forecast for the MAS score based on a statistical assessment. We can demonstrate 4x runtime improvement while incurring minor tradeoffs for accuracy.

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<title>Framework for identifying recommended rules and DFM scoring model to improve manufacturability of sub-20nm layout design</title>

Cited by 11 publications

References 0 publications

Design for manufacturability (DFM) physical verification using machine learning

Design for manufacturability (DFM) physical verification using machine learning

Decomposition-aware layout optimization for 20/14nm standard cells

Machine learning architecture evaluation for fast and accurate weak point detection

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