CMOS-based imaging system-on-chip (i-SoC) technology is successfully producing large monolithic and hybrid FPAs that are superior in many respects to competing CCD-based imaging sensors. The hybrid approach produces visible 2048 by 2048 FPAs with <6 e-read noise and quantum efficiency above 80% from 400 nm to 920 nm; 4096 by 4096 mosaics are now being developed. The monolithic approach produces visible 12-bit imaging system-on-chips such as a 1936 by 1088 with higher quantum efficiency than mainstream CCDs, <25 e-read noise, <0.02% fixed pattern noise, automatic identification and replacement of defective pixels, black-level clamping, total power dissipation of only 180 mW, and various programmable features. Several successors having ≥12 Mpixels are in development. In both cases low-light-level performance is boosted by coupling the sensors to image intensifiers.