Large area visible arrays: performance of hybrid and monolithic alternatives

Kozlowski, Lester J.; Bai, Yibin; Loose, Markus; Joshi, Atul; Hughes, Gary W.; Garnett, James D.

doi:10.1117/12.456758

Cited by 14 publications

(6 citation statements)

References 12 publications

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“…HCDs have much smaller capacitive loads that involve low power CMOS switches. 20 A typical 1024 x 1024 pixel 2 H1RG HCD, which uses a source follower amplifier in each pixel, has been shown to use ∼200 mW for all bias clock generation and readout. 21 The CTIA amplifier and in-pixel comparator used in the Speedster-EXD pixel design (see Section 4) use more power per pixel than a simple source follower amplifier.…”

Section: Hybrid Cmos Detectorsmentioning

confidence: 99%

Speedster-EXD: a new event-driven hybrid CMOS x-ray detector

Griffith

Falcone

Prieskorn

et al. 2016

J. Astron. Telesc. Instrum. Syst

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The Speedster-EXD is a new 64x64 pixel, 40 µm pixel pitch, 100 µm depletion depth hybrid CMOS X-ray detector (HCD) with the capability of reading out only those pixels containing event charge, thus enabling fast effective frame rates. A global charge threshold can be specified, and pixels containing charge above this threshold are flagged and read out. The Speedster detector has also been designed with other advanced in-pixel features to improve performance, including a low-noise, high-gain CTIA amplifier that eliminates interpixel capacitance crosstalk (IPC), and in-pixel Correlated Double Sampling (CDS) subtraction to reduce reset noise. We measure the best energy resolution on the Speedster-EXD detector to be 206 eV (3.5 %) at 5.89 keV and 172 eV (10.0 %) at 1.49 keV. The average IPC to the four adjacent pixels is measured to be 0.25 ± 0.2 % (i.e. consistent with zero). The pixel-to-pixel gain variation is measured to be 0.80 ± 0.03 %, and a Monte Carlo simulation is applied to better characterize the contributions to the energy resolution.

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Section: Hybrid Cmos Detectorsmentioning

confidence: 99%

Speedster-EXD: a new event-driven hybrid CMOS x-ray detector

Griffith

Falcone

Prieskorn

et al. 2016

J. Astron. Telesc. Instrum. Syst

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“…The bulk of the detector array is nearly fully depleted, delivering excellent QE at long wavelengths and good MTF characteristics (Kozlowski et al, 2002) since the diffusion crosstalk is negligible. The back-illuminated detector array is bump bonded to a CMOS multiplexer with a bump in each pixel.…”

Section: Silicon P-i-n Detector Arraysmentioning

confidence: 99%

CCD Technology

Burke¹,

Jorden²,

Vu³

2006

Exp Astron

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Charge-coupled devices (CCDs) continue to reign supreme in the realm of imaging out to 1 μm, with the steady improvement of performance and the introduction of innovative features. This review is a survey of recent developments in the technology and the current limits on performance. Device packaging for large, tiled focal-plane arrays is also described. Comparisons between CCDs and the emerging CMOS imagers are highlighted in terms of process technology and performance.

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“…CTIA is a low noise, high speed input circuit; and DI circuit is more suitable to mid to high background, high-speed application. Figure 6 shows the mean read noise measured from CMOS-based imaging sensors for representative low-noise input circuits 11 . The plot shows that noise is a strong function of effective sense capacitance at the input node.…”

Section: Read Noise Dark Current and Dynamic Rangementioning

confidence: 99%

Hybrid CMOS focal plane array with extended UV and NIR response for space applications

et al. 2004

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Silicon-based hybrid CMOS focal plane array technology offers many advantages needed for both ground-based and space imaging applications. These advantages include enhanced UV and NIR sensitivity, extensive on-chip readout capability, inherent radiation hardness, flexible imaging readout and the ability to provide extremely low noise at high video rates. For infrared imaging applications that involve UV-through visible channels, the readout electronics commonality facilitates a great simplification to system designs. In this paper, Rockwell Scientific CMOS-based hybrid silicon FPA technology and the recent progress are presented. The hybrid FPAs developed include 640x480, 1024x1024 and 2048x2048 formats with pixel sizes ranging from 27 m to 18 m square, featuring a high optical fill factor (~100%), broad-band response (200nm to 1000nm) with high quantum efficiency, and low read noise (<6e-) that approaches astronomy CCDs at 100KHz video rate and surpasses astronomy CCDs at 1MHz rate. Other performance parameters, such as spatial uniformity, dark current, pixel crosstalk/MTF and CMOS features are also discussed. SENSOR TECHNOLOGY FOR SPACE APPLICATION CCD and CMOSThe key requirements for a sensor assembly to operate in space environments are high reliability, low weight, low power and high tolerance to radiation damage. Since its invention in 1969 1 , silicon charge-coupled device (CCD) has improved in performance and built its flight heritage. Both size and format of CCDs have increased in the past several years for much-improved field-of-view and imaging resolution. This technology has been made available for various space missions, such as Galileo spacecraft 2 and Hubble Space Telescope 3 . However, concerns about CCDs in space exist due to charge transfer degradation in radiation environments, excessive power consumption, blooming and image smearing.CMOS-based monolithic image sensor is another class of solid-state electronic imaging sensor that is rapidly evolving along with the advances in modern sub-micron CMOS technology. CMOS sensors offer important solutions to the CCD limitations encountered for use in orbit. The operation of CMOS sensors requires only one charge transfer (pixel-based charge-to-voltage conversion) for signal readout, consumes a very low power (typically operated at 3.3V and lower), and enables miniature cameras with on-chip integration of analog and digital circuitry, which significantly reduces the system mass, volume and complexity. In addition, the CMOS sensor can operate in a wide temperature range (cryogenic to 350K). CMOS wafer fabrication can use the mainstream commercial semiconductor foundries, and the cost of fabricating a monolithic 200mm CMOS wafer is less than that of a 150mm wafer using a specialized CCD process. More importantly, the CMOS imager is inherently tolerant to radiation damage. Space missions employing CMOS sensors, such as Deep Space-1 (256x256 format APS) 4 and TEAMSAT (512x512 format APS) 5 , have provided encouraging science data and high contrast images.Ad...

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Large area visible arrays: performance of hybrid and monolithic alternatives

Cited by 14 publications

References 12 publications

Speedster-EXD: a new event-driven hybrid CMOS x-ray detector

Speedster-EXD: a new event-driven hybrid CMOS x-ray detector

CCD Technology

Hybrid CMOS focal plane array with extended UV and NIR response for space applications

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