&lt;title&gt;Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems&lt;/title&gt;

Savaria, Yvon; Bois, Guy; Popovic, Pierre; Wayne, Andrew J.

doi:10.1117/12.255817

Cited by 3 publications

(1 citation statement)

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“…Two Virtual Processing Elements (VPEs), from Xilinx XC4013E family, constitute the computing core of X-CIM. These components can˝be automatically reconfigured to replicate different dedicated hardware in less than 30 ms [6]. X-CIM is targeted for application development strategy that is based on a hardware-software co-design methodology.…”

Section: Fft Core Function On X-cim Boardmentioning

confidence: 99%

Self-sorting radix-2 FFT on FPGAs using parallel pipelined distributed arithmetic blocks

Shaditalab

Bois

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)

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Design and implementation of parallel pipelined Fast Fourier Transform (FFT), using Decimation in Frequency (DIF) algorithm on FPGA's is presented. The FFT core for 1024 complex data point is implemented on the X-CIM which is a Re-configurable Acceleration Subsystem (RAS) with a TMS320C4x DSP-processor and two XC4013 FPGA as its processing units. The proposed FFT machine is˝an alternative to the bit serial-parallel FFT algorithm using Distributed Arithmetic Look Up Table (DALUT) method. The advantage of proposed design is mainly in its cost effective and hardware-efficient parallel implementations of the N-point DFT, offering highly attractive throughput rates in relation to the conventional DSP processors. Moreover, the processor's data-path structure is independent of sampled data-points, and it has a self-sorting property where the output is in properly ordered form. Our goal is to improve size-performance requirements of an FFT core function using modular and hierarchical VHDL description combined with IP_Core library elements from Xilinx.

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Section: Fft Core Function On X-cim Boardmentioning

confidence: 99%