LSSD Compatible and Concurrently Testable Ram

Maeno, H.; Nii, K.; Sakayanagi, S.; Kato, S.

doi:10.1109/test.1992.527881

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Reducing the Test Time1

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Cited by 4 publications

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“…Maeno et a1 [5] proposed a scheme to reduce the time taken for these operations. For common test algorithms such as the Marching Test, the data to be written stays constant for long periods of time during testing, whereas the address needs to be changed very frequently.…”

Section: Reducing the Test Timementioning

confidence: 99%

Embedded RAM testing

Franklin

Saluja

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing

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Embedded RAMs are RAMs, whose address, data, and read/write controls can not be directly controlled or observed through the chip's 1/0 pins. Testing these memories, which are incorporated on a large percentage of VLSI devices, is naturally harder because of the lack of controllability of its inputs and observability of its outputs. Testing such RAMs is the theme of this paper. It brings to light the challenges involved in testing embedded RAMs, and discusses techniques such as design for testability (DFT) and built-in self test (BIST), which help in improving the testability of these RAMs.

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Section: Reducing the Test Timementioning

confidence: 99%