Is there any future for deterministic self-test of embedded RAMs?

Krasniewski, Andrzej; Gaj, K.

doi:10.1109/etc.1993.246521

Cited by 8 publications

(1 citation statement)

References 24 publications

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“…Although high-speed self-test circuits for memories exist, most have been dependent upon pseudorandom patterns [2]. This approach can be helpful in finding non-target-type defects [3] but, for well-understood defect sets, deterministic test patterns are superior. The exact patterns needed to exercise and find the defects can be further simplified because the memory configurations are understood.…”

Section: Introductionmentioning

confidence: 99%

A 370-MHz memory built-in self-test state machine

Adams¹,

Connor²,

Koch³

et al.

Proceedings the European Design and Test Conference. ED&TC 1995

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Hardware and simulation results for a 370-MHz memory built-in self-test state machine are presented. Dynamic differential cascode voltage switch logic, unique clocking techniques, and logic pipelining were used to achieve the 370-MHz performance. Testing of multiple SRAMs and content addressable memories is accomplished with deterministic patterns generated by the state machine. Inclusion of a programmable pattern implemented via scan initialization provides test-pattern flexibility. Failing addresses are stored for redundancy implementation.

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Section: Introductionmentioning

confidence: 99%

A 370-MHz memory built-in self-test state machine

Adams¹,

Connor²,

Koch³

et al.

Proceedings the European Design and Test Conference. ED&TC 1995

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David

Brzozowski

Jürgensen

1997

Journal of Electronic Testing

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Memory BIST with address programmability

Fradi

Nicolaidis

Anghel

2011

2011 IEEE 17th International on-Line Testing Symposium

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ISBN 978-1-4577-1053-7International audienceIn modern SoCs embedded memories concentrate the majority of defects. In addition defect types are becoming more complex and diverse and may escape detection during fabrication test, leading to field failures due to the use of faulty components in final products. As a matter of fact memories have to be tested by test algorithms achieving very high fault coverage for a increasingly complex faults. Fixing the test algorithm during the design phase may not be compatible with this goal, as unexpected failures not covered by this algorithm may be occur during production. Also, having the possibility to select the memory test algorithm after fabrication is very important during the initial phase of a new process node (both process debug and production ramp-up). Programmable BIST approaches, allowing selecting after fabrication a large variety of memory tests, are therefore desirable, but may lead on unacceptable area cost. BIST approaches enabling test algorithm programmability and data background programmability at low area cost have been presented in the past. However, no proposals exist for programming the address sequence used by the test algorithm. In this paper we expend programmable BIST to include address programmability. This new feature is implemented at low cost by using the memory under test itself to store the desired address sequence and some compact circuitry that enables using this sequence for testing the memory

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Is there any future for deterministic self-test of embedded RAMs?

Cited by 8 publications

References 24 publications

A 370-MHz memory built-in self-test state machine

A 370-MHz memory built-in self-test state machine

Untitled

Memory BIST with address programmability

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