LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors

Lira, Javier; Molina, Carlos; González, Antonio

doi:10.1109/iccd.2009.5413142

Cited by 12 publications

(8 citation statements)

References 24 publications

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“…In the same work an analysis of the balance between static and dynamic power for NUCA architectures and an energy/performance trade-off evaluation for NUCA and its comparison with UCA is also given concluding that the static components dominate energy dissipation in NUCA designs, making the reduction of static power consumption a substantial issue for NUCA caches in deep sub-micron CMOS processes. The energy model is presented only for single core systems, however some works [23][24] [25] have proposed the use of that model also for CMP NUCA systems, showing the relevance of the need for a CMP NUCA energy model. In [21] a model for NUCA interbank network elements is devised.…”

Section: Related Workmentioning

confidence: 99%

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Energy Behaviour of NUCA Caches in CMPs

Bardine

Foglia

Panicucci

et al. 2011

2011 14th Euromicro Conference on Digital System Design

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Advances in technology of semiconductor make nowadays possible to design Chip Multiprocessor Systems equipped with huge on-chip Last Level Caches. Due to the wire delay problem, the use of traditional cache memories with a uniform access time would result in unacceptable response latencies. NUCA (Non Uniform Cache Access) architecture has been proposed as a viable solution to hide the adverse impact of wires delay on performance. Many previous studies have focused on the effectiveness of NUCA architectures, but the study of the energy and power aspects of NUCA caches is still limited. In this work, we present an energy model specifically suited for NUCA-based CMP systems, together with a methodology to employ the model to evaluate the NUCA energy consumption. Moreover, we present a performance and energy dissipation analysis for two 8-core CMP systems with an S-NUCA and a D-NUCA, respectively. Experimental results show that, similarly to the monolithic processor, the static power also dominates the total power budget in the CMP system.

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Section: Related Workmentioning

confidence: 99%

“…In [22], an energy model is defined for a single core NUCA based architecture, taking into account both static and dynamic contributions of NUCA caches. In [23] [24][25] the model proposed in [22] is employed to evaluate energy aspects of proposed solution in CMP environment.…”

Section: Introductionmentioning

confidence: 99%

Energy Behaviour of NUCA Caches in CMPs

Bardine

Foglia

Panicucci

et al. 2011

2011 14th Euromicro Conference on Digital System Design

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“…By identifying key data structures statically, Whirlpool can place data without wasting resources in learning how data is used. By contrast, many prior schemes that achieve a similar data placement do so by migrating data on demand [18,43,68]. The extra data movement from migrations can exceed the energy savings of smart data placement (see Sec.…”

Section: Triangles Vertices Pointsmentioning

confidence: 99%

Whirlpool

Mukkara

Beckmann

Sánchez

2016

SIGARCH Comput. Archit. News

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Cache hierarchies are increasingly non-uniform and difficult to manage. Several techniques, such as scratchpads or reuse hints, use static information about how programs access data to manage the memory hierarchy. Static techniques are effective on regular programs, but because they set fixed policies, they are vulnerable to changes in program behavior or available cache space. Instead, most systems rely on dynamic caching policies that adapt to observed program behavior. Unfortunately, dynamic policies spend significant resources trying to learn how programs use memory, and yet they often perform worse than a static policy. We present Whirlpool, a novel approach that combines static information with dynamic policies to reap the benefits of each. Whirlpool statically classifies data into pools based on how the program uses memory. Whirlpool then uses dynamic policies to tune the cache to each pool. Hence, rather than setting policies statically, Whirlpool uses static analysis to guide dynamic policies. We present both an API that lets programmers specify pools manually and a profiling tool that discovers pools automatically in unmodified binaries. We evaluate Whirlpool on a state-of-the-art NUCA cache. Whirlpool significantly outperforms prior approaches: on sequential programs, Whirlpool improves performance by up to 38% and reduces data movement energy by up to 53%; on parallel programs, Whirlpool improves performance by up to 67% and reduces data movement energy by up to 2.6×. CCS Concepts • Computer systems organization → Multicore architectures.

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“…Kim et al [50] were the first to propose a static NUCA (S-NUCA) architecture where a network of cache banks were used to reduce average access latency. Since then, NUCA-based memory hierarchies have been extensively studied in the architecture community [62], [21], [32].…”

Section: A Distributed Cache-based Memory Memoriesmentioning

confidence: 99%

Software Controlled Memories for Scalable Many-Core Architectures

Bathen

Dutt

2012

2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications

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Technology scaling along with the ever evolving demand for media-rich software stacks have motivated the need for many-core platforms. With the increase in compute power and its inherent demand for high memory bandwidth comes the need for vast amounts of on-chip memory space. Thus, designers must carefully provision the memory real-estate to meet their application's needs. It has been shown in the embedded systems domain that both software controlled memories (e.g., scratchpad memories) and hardware-controlled memories (e.g., caches) have their pros and cons, some application domains such as multimedia fit very well in the software-controlled memory model, while other domains such as databases work well with caches. As a result, efficient memory management is extremely critical as it has a great impact on the system's power consumption and throughput. Traditional memory hierarchies primarily consist of SRAM-based onchip caches, however, with the emergence of non-volatile memories (NVMs) and mixed-criticality systems, on-chip memories will be heterogeneous, not only in type (cache vs. scratchpad) but also in technology (e.g., SRAM vs. NVM). This paper surveys the state of the art in memory subsystems for many-core platforms, and presents strategies for efficiently managing software-controlled memories in the many-core domain, while addressing the various challenges designers face in deploying such memory subsystems (e.g., sharing the memory resources, accounting for variations in the subsystem, etc.).

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LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors

Cited by 12 publications

References 24 publications

Energy Behaviour of NUCA Caches in CMPs

Energy Behaviour of NUCA Caches in CMPs

Whirlpool

Software Controlled Memories for Scalable Many-Core Architectures

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