Lowering the Error Floor of LDPC Codes Using Multi-Step Quantization

A new two‐stage decoding scheme with unreliable path search to lower the error‐floor for low‐density parity‐check codes

“…Among the researches which do not require the prior information of dominant trapping sets, two-stage decoding schemes have been one of the popular decoding procedures to deal with the error-floor [10][11][12][13][14]. Two-stage decoding schemes usually consist of two decoding steps, the conventional belief propagation (BP) decoding as the first-stage decoding and the re-decodings with manipulated log-likelihood ratios (LLRs) of variable nodes as the second-stage decoding.…”

“…However, determining a proper value of N is quite sensitive to decoding performance for the given code parameters. For a fixed-point implementation, multi-step quantisation scheme is proposed to lower the error-floor [14], which is based on successive re-quantisation and re-decoding of the input blocks to avoid harmful trapping sets while keeping the same number of quantisation bits.…”

High Speed Low Error Floor Hardware Implementation and Fast and Accurate Error Floor Estimation of LDPC Decoders

“…Trapping sets are normally classified by a pair (a, b), in which a is the number of variable nodes whose induced subgraph has b check nodes of odd degree [10,16,48,49,[54][55][56][57][58][59]. Trapping sets with smaller values of a and b are generally believed to be more harmful to iterative decoding.…”

Error Floor Analysis of Quasi-Cyclic LDPC and Spatially Coupled-LDPC Codes and Construction of Codes with Low Error Floor

“…As a result of the above discussion, it is crucial to improve the error floor performance either in block LDPC codes or SC-LDPC codes. Generally speaking, reducing the error floor is possible by means of two main approaches: (1) modification on the decoding algorithm to improve the error rate performance [51], [96], [93], [85], and (2) new construction of codes with a set of desired properties. In our work, we focus on the second approach to design either quasi-cyclic LDPC block codes or spatially coupled LDPC codes with low error floor.…”