Low-voltage ULSI design

Shimohigashi, K.; Seki, Kazuhiko

doi:10.1109/4.210022

Cited by 36 publications

(7 citation statements)

References 15 publications

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“…Several BiCMOS logic structures are reported in the literature for designing complex VLSI systems based on primitive cells, such as, inverter, buffer, multi-input NAND and NOR gates etc., [24]. These Depending on the type of the arithmetic function to be implemented, it is essential to exploit the advantages of both the CMOS and BiCMOS logic schemes.…”

Section: Architecture Design Using Bicmos Logicmentioning

confidence: 99%

A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications

Poornaiah¹,

Mohan²,

Ahmad

1993

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting BIPOL-93

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In this paper, we present the design of a novel BiCMOS/Bipolar concurrent multiplier-accumulator (BICMAC) architecture that can be configured on-the-fly for selecting multiply alone or multiplyaccumulation (add/subtract) computations involving unsigned/signed 2's compliment/mixed-mode data formats for normal as well as extended precision arithmetic. The proposed BICMAC does not require the use of a separate adder module normally used in the conventional MACS thereby achieving approximate reductions of 50% and 20%, respectively, in the computation time and area making it attractive for VLSI implementation. It can be used as a fundamental computing block of the algorithmically specialized integrated circuits, like, systolic and wavefront array processors for an efficient implementation of the computationally intensive DSP functions: FIRDIR filtering, correlation, matrix multiplication etc., resulting in reduced hardware complexity and latency. The technology independent nature of the proposed architecture makes it attractive also for VLSI implementation using fast emerging contemporary technologies: GaAs (MESFET, HEMT, JET) and HBT.

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Section: Architecture Design Using Bicmos Logicmentioning

confidence: 99%

A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications

Poornaiah¹,

Mohan²,

Ahmad

1993

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting BIPOL-93

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“…The fundamental opportunity of quasiadiabatic microelectronics is based on the second law of thermodynamics, which can be stated as follows: In any thermodynamic process that proceeds from one equilibrium state to another, the entropy of a closed system either remains unchanged or increases [59]. Entropy change dS can be expressed as Quasi-Adiabatic Switching dQ/T = dS>0 (44) where dQ is the heat added to the system and T is its absolute temperature. In a computational process, it is only those steps that discard information or increase disorder and therefore increase entropy (dS> 0) which have a lower limit on energy dissipation or heat generation (dQ > 0) imposed by the second law of thermodynamics [4], [5].…”

Section: Quasi-adiabatic Microelectronicsmentioning

confidence: 99%

“…The two key requirements for quasi-adiabatic or asymptotically zero dissipation digital microelectronics are summarized by (44) and (47): information cannot be destroyed and quasi-equilibrium operation must prevail [59], [60]. These requirements can be reflected in a hierarchy of limits on quasi-adiabatic microelectronics as illustrated in Fig.…”

Section: Quasi-adiabatic Microelectronicsmentioning

confidence: 99%

Low power microelectronics: retrospect and prospect

1995

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“…Therefore, we can design a compact and low-power architecture for the unified message compression unit, which reduces the numbers of adder chains. In the SHA-1 computation, register e is used for the storage of the temporary addition values T= S 5 Another important part of the compact and unified SHA-1 and SHA-256 hardware is a message scheduler that generates message dependant words W t used as an input data for each step of round operation of the message compression unit. The message scheduler is the most expensive part of SHA hardware in terms of hardware resources.…”

Section: Unified Sha-1 and Sha-256 Hardware Modulementioning

confidence: 99%

“…So, the maximum current value of USIM is not directly used for MTM. The dynamic power dissipation of a CMOS circuit is given by [5]:…”

Section: Requirements For Cryptographic Enginementioning

confidence: 99%

Design of Cryptographic Hardware Architecture for Mobile Computing

Kim¹,

Kim²,

Cho³

2009

Journal of Information Processing Systems

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This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

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Low-voltage ULSI design

Cited by 36 publications

References 15 publications

A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications

A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications

Low power microelectronics: retrospect and prospect

Design of Cryptographic Hardware Architecture for Mobile Computing

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