Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors

Ghasemi, Hamid; Draper, Stark C.; Kim, Nam Sung

doi:10.1109/hpca.2011.5749715

Cited by 20 publications

(30 citation statements)

References 21 publications

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“…Architectures designed specifically to take advantage of low voltage properties such as fast caches relative to logic have been proposed by Zhai et al [39] and Dreslinski et al [9]. Other work has focused on improving the reliability of large caches in low voltage processors [11,29]. While significant progress has been made in bringing this technology to market, including a prototype processor from Intel [38], many challenges remain, including reliability and high variation.…”

Section: Low Voltage Designsmentioning

confidence: 99%

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips

Miller

Pan

Thomas

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

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Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process variation, which can lead to large differences in the maximum frequency achieved by individual cores. This paper presents Booster, a simple, low-overhead framework for dynamically rebalancing performance heterogeneity caused by process variation and application imbalance. The Booster CMP includes two power supply rails set at two very low but different voltages. Each core can be dynamically assigned to either of the two rails using a gating circuit. This allows cores to quickly switch between two different frequencies. An on-chip governor controls the timing of the switching and the time spent on each rail. The governor manages a "boost budget" that dictates how many cores can be sped up (depending on the power constraints) at any given time. We present two implementations of Booster: Booster VAR, which virtually eliminates the effects of core-to-core frequency variation in near-threshold CMPs, and Booster SYNC, which additionally reduces the effects of imbalance in multithreaded applications. Evaluation using PARSEC and SPLASH2 benchmarks running on a simulated 32-core system shows an average performance improvement of 11% for Booster VAR and 23% for Booster SYNC.

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Section: Low Voltage Designsmentioning

confidence: 99%

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips

Miller

Pan

Thomas

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

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“…Ghasemi et al propose the use of heterogeneous cell sizes, in order that when operating at low voltages, ways or sets of small SRAM cells are deactivated if they start to fail [17]. Khan et al propose a mixed-cell memory design, where some of the cells are more robust and failure-resistant and, therefore, more reliable candidates to store dirty cache blocks, while the rest are designed using traditional cells [21].…”

Section: Related Workmentioning

confidence: 99%

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Ferrerón

Gracia

Alastruey-Benedé

et al. 2016

IEEE Trans. Comput.

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Abstract-Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100% of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression-and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2%, even when using small SRAM cells, which implies over 90% of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.

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“…An effective way to reduce power consumption is voltage scaling. Unfortunately, as supply voltage decreases into the ultra-low voltage regime, the failure rate of circuits increases dramatically [1]. This failure rate worsens as technology scales, due primarily to the everincreasing process variation [2].…”

mentioning

confidence: 99%

Reliable ultra-low voltage cache with variation-tolerance

Zhang

Ampadu

2013

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

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In this paper, an ultra-low voltage cache with improved variation-tolerance is proposed. A fast and stable adaptive mechanism, able to dynamically adjust error control strength, is designed to make the cache more resilient to supply voltage variations. Our proposed method shows a 10X improvement in residual error rate at ultra-low voltage, compared to an adaptive ECC method. It also reduces residual error rate by 3X compared to variable strength ECC method at low voltage operation and has less storage overhead.I.

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Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors

Cited by 20 publications

References 21 publications

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Reliable ultra-low voltage cache with variation-tolerance

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