2015
DOI: 10.1007/s10853-015-9301-9
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Low-voltage ferroelectric–paraelectric superlattices as gate materials for field-effect transistors

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Cited by 9 publications
(5 citation statements)
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“…The insulating buffer layer thickness is usually designed to optimize capacitance matching 87,88 ; however, the optimization of this para meter is typically based on a model assuming homogen eous polarization, which is not valid for the multidomain case, in which the NC in the ferroelectric is approx imately independent of the dielectric layer thickness above a certain value. Thus, further device modelling that explicitly considers multidomain gates with mobile domain walls is required 89,90 .…”
Section: Device Implementation Work On Ferroelectric Fetsmentioning
confidence: 99%
“…The insulating buffer layer thickness is usually designed to optimize capacitance matching 87,88 ; however, the optimization of this para meter is typically based on a model assuming homogen eous polarization, which is not valid for the multidomain case, in which the NC in the ferroelectric is approx imately independent of the dielectric layer thickness above a certain value. Thus, further device modelling that explicitly considers multidomain gates with mobile domain walls is required 89,90 .…”
Section: Device Implementation Work On Ferroelectric Fetsmentioning
confidence: 99%
“…We use the word “paradoxical” here as the depolarization fields naturally emanating from the mechanism prescribed above have long been perceived as detrimental in the development of FE-gated MOSFET structures designed to possess a memory where the memory function is basically fulfilled by the degenerate polarization states the FE gate can take on, allowing for binary data storage. In fact, artificial superlattices composed of repeating units of an FE/DE stack were initially considered as high- k structures for capacitors integrable into SC-based devices or as tunable layers that tailor the depolarization fields. In this picture, FE/DE layer thickness ratios become the main foothold of controlling the polar to nonpolar transition temperature of the stack. If the layer ratios are chosen carefully for a background misfit induced by the substrate, the transition temperature of the superlattice can be engineered so as to give a maximal dielectric response or even a stable single-domain state. , The sensitivity of these structures to the mechanical/electrostatic boundary conditions (BCs) and layer sequence relative to the electrodes have been shown explicitly in earlier analytical works. , Apart from all of the aforementioned data, the polarization and the internal fields inside the FE layers when interfacing a DE are long predicted to be antiparallel, which conforms well to the recently and frequently mentioned negative capacitance (NC) phenomena.…”
Section: Introductionmentioning
confidence: 99%
“…This is followed by three theoretical/computational studies. Misirlioglu et al report a thermodynamic modeling study which demonstrates that ferroelectric-paraelectric superlattice heterostructures can exhibit on/off switching properties at much lower bias voltages than in a linear high dielectric constant gate [45]. They propose that such constructs can be employed as gate materials for field effect transistors.…”
mentioning
confidence: 99%
“…Using a similar methodology, Sun et al address the question ''Are ferroelectric multilayers capacitors in series?'' and demonstrate that the answer is ''No'' except in cases where both ferroelectrics are dielectrics, or the individual layers are screened from one another [46]. In the fourth paper, Chen et al use density functional theory computations to calculate the barriers to charge injection at metal/polyethylene interfaces [47].…”
mentioning
confidence: 99%