Low Voltage and Low Power Pulse Flip-Flops in Nanometer CMOS Processes

Hu, Jianping; Yu, Xiaoying

doi:10.2174/1573413711208010102

Cited by 13 publications

(10 citation statements)

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“…One of the most important features in MCML circuits is that their energy dissipation is independent of frequency, and their value can be calculated by formula (3). Therefore, in No-power-gating MCML blocks, the energy loss can be acquired easily.…”

Section: Energy Dissipationsmentioning

confidence: 99%

“…However, with the CMOS technology scaling into deep sub-micro processes, leakage consuming catches up with the dynamic power dissipation. The leakage consumption has become one of the most important factors in low-power hardware [3]. From (1), E leakage decreases linearly with the reduction of source voltage V DD .…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, power gating techniques have widely been addressed to reduce standby power dissipations [3,4].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

Geng¹,

Hu²,

Zou³

2014

TOEEJ

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Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons between conventional MCML and proposed power-gating MCML circuits are carried out. The 1-bit MCML full adder based on the proposed scheme nearly saves 36% of energy dissipations with respect to no-power-gating MCML one, for a power-gating activity of 0.6. Moreover, the proposed power-gating MCML circuit also has a great advantage in power dissipations in high frequency regions compared with the power-gating static CMOS ones. The power consumption of the MCML 1-bit full adder based on the proposed scheme is 63.2%, 44.8%, and 36.97% compared with the powergating static CMOS one when the operating frequency is 1GHz, 1.5GHz, and 2GHz, respectively.

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Section: Energy Dissipationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

Geng¹,

Hu²,

Zou³

2014

TOEEJ

Self Cite

View full text Add to dashboard Cite

show abstract

“…With the increasing demand for battery-operated mobile platforms like laptops, and biomedical applications that require ultra-low power dissipations, low power designs have become more and more important. IC designers work hard on high performance with low power dissipation and small area [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Research on Ring Fire Diagnosis of DC Motor Based on Discrete Wavelet Lipschitz Index

Zhao-ping¹,

Yang²,

Tang³

et al. 2015

TOEEJ

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Scaling supply voltage of FinFET circuits is an efficient method to achieve low power dissipation. Superthreshold FinFET logic circuits can attain low power consumption with favorable performance, because FinFET devices operating on medium strong inversion regions can provide better drive strength than conventional CMOS transistors. The supply voltage of the super-threshold circuit is much larger than threshold voltage of the transistors, but it is lower than normal standard supply voltage. In this paper, basic FinFET logic gates based on static logic, DCVSL (Differential Cascode Voltage Switch Logic), PTL (Pass Transistor Logic), and TG (Transmission Gate) logic styles operating on medium strong inversion regions are investigated in terms of power consumption and delay. All circuits are simulated with HSPICE at a PTM (Predictive Technology Model) 32nm FinFET technology. The simulation results show that superthreshold FinFET logic gates operating on medium strong inversion regions attain about 41% power reduction with a penalty of only about 23%.

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“…Lowering the supply voltage is an effective method to reduce power consumption, since the dynamic and leakage dissipations decrease quadratically and linearly as supply voltage scales down, respectively [7][8][9][10][11]. Sub-threshold or near-threshold circuits can achieve low energy consumption, since their supply voltage is below or slightly above the threshold voltage of the transistors [10].…”

Section: Introductionmentioning

confidence: 99%

Low-power Super-threshold FinFET Domino Logic Circuits for High- Speed Applications

Bo¹,

Hu²,

Li³

et al. 2014

TOAUTOCJ

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Domino logic circuits have faster operating speed than commonly used static logic ones, because they have lower input capacitances and no contention during transition. However, Domino logic circuits have more power dissipation than static logic ones, since their clock tress with high switch activity dissipates large energy. A low-power superthreshold computing scheme is proposed to reduce power dissipations of FinFET Domino logic circuits. The pull-down transistors of all FinFET Domino circuits are configured in parallel, and thus improve operating speed. Unlike nearthreshold circuits, super-threshold ones are supplied by much a larger supply voltage than the threshold voltage, but it is lower than the standard supply voltage. Super-threshold FinFET logic circuits can attain low power consumption with favorable performance, because FinFET devices operating on medium strong inversion regions can provide better drive strength than conventional CMOS ones. The basic Domino logic gates are compared with static logic ones in terms of energy consumption, delay, energy delay product (EDP), and maximum operation frequency with different voltages from near-threshold to super-threshold regions. All circuits are simulated with HSPICE at a PTM (Predictive Technology Model) 32nm FinFET technology. The results show that the Domino gates can operate faster than static ones. In addition, it is also shown that Domino gates exhibit the best EDP in super-threshold regions (about 700mV). Compared with the standard supply voltage of 1.0 V, the Domino gates supplied by 0.8V can attain energy reductions of more than 38.3% with a small performance penalty of about 14%.

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Low Voltage and Low Power Pulse Flip-Flops in Nanometer CMOS Processes

Cited by 13 publications

References 0 publications

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

Research on Ring Fire Diagnosis of DC Motor Based on Discrete Wavelet Lipschitz Index

Low-power Super-threshold FinFET Domino Logic Circuits for High- Speed Applications

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