Low-voltage adders for power-efficient arithmetic circuits

Margala, Martin

doi:10.1016/s0026-2692(99)00048-8

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Cited by 6 publications

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“…Increasing demand for faster, smaller, cheaper and less in need of battery recharge, portable electronic devices, has encouraged researchers to work on different optimization methods both in high level [1,2] and low level [3,4] design sequences.…”

Section: Introductionmentioning

confidence: 99%

A novel adder cell for ultra low voltage, ultra low power networks in nanoscale VLSI circuits

Karimi

Sadeghi

2011

IEICE Electron. Express

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Abstract:A novel full adder cell is designed so that it can overcome the challenges of circuit design in deep submicron (DSM) technology. The proposed adder cell utilizes multiplexing control input techniques (MCIT) for the sum operation and uses a new arrangement of pass transistors for carry operation. The adder is then used in an 8×8 bit Braun-array multiplier to show its performance. The layout of multiplier is simulated in 32 nm CMOS technology by Microwind31 (MW31) VLSI CAD TOOL. Simulated results show that our circuit operates properly in nanoscale and has a very small area.

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