Low-Voltage 0.81mW, 1–32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection

Abstract

A CMOS low-voltage amplifier with approximately constant bandwidth and DC rejection is introduced. The design is based on the cascade of a wide linear input range OTA and an op-amp and a servo-loop with extremely large time constants. It operates with ±0.45V supplies and a power consumption of 0.81mW in 180nm technology. The bandwidth changes only from 9.08MHz to 9.54MHz over a gain range from 1 to 32, it has a 9.8Hz low cutoff frequency and a DC attenuation of 38dBs. DC floating voltage sources are used to keep the gates of all differential pairs at a constant value close to a supply rail in order to operate the amplifier circuit with minimum supply voltage. The proposed circuit has small and large signal figures of merit F OM SS = 5380 (MHz*pF/mW) and F OM LS = 0.0085((V/ns)*pF/mA) for a nominal gain A=32.

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

“…It is denoted as a class A/AB amplifier, since the input stage operates in class A and the output stage in class AB. Other examples of class A/AB amplifiers can be found in [26,27].…”

Design and Analysis of a High Gain, Low-Noise and Low-Power Analog Front End for ECG Acquisition in 45nm Technology Using Gm/Id Method

“…Although digital circuits has already been working on technology nodes (interchangeable with channel length) lower than 5nm[1,2], their analog circuit counterparts did not advance at the same pace. For the past two decades, most of the analog circuits has been developed using 180 nm node or above [3][4][5][6][7][8][9][10][11][12][13][14][15][16] because of some benefits enjoyed by the larger technology nodes, for example, ease of design, larger amplification etc. However, in mixed-signal circuits, analog circuits need to be fabricated with the digital circuits on the same chip to meet various purposes [17].…”

Design and Analysis of a High-Gain, Low-Noise, and Low-Power Analog Front End for Electrocardiogram Acquisition in 45 nm Technology Using gm/ID Method

“…Although digital circuits have already been working on technology nodes (interchangeable with channel length) lower than 5 nm [1,2], their analog circuit counterparts have not advance at the same pace. For the past two decades, most analog circuits have been developed using a 180 nm node or above [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17] due to some benefits enjoyed by the larger technology nodes, for example, ease of design, larger amplification, low noise, etc. However, in mixed-signal circuits, analog circuits need to be fabricated with the digital circuits on the same chip to meet various purposes [18].…”