No abstract

A full CMOS seventh-order linear phase filter based on-biquads with a 3-dB frequency of 200 MHz is realized in 0.35-m CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both low-distortion figures and high-frequency operation. The common-mode feedback (CMFB) employed takes advantage of the filter architecture; incorporating the load capacitors into the CMFB loop improves further its phase margin. A very simple automatic tuning system corrects the filter deviations due to process parameter tolerances and temperature variations. The group delay ripple is less than 5% for frequencies up to 300 MHz, while the power consumption is 60 mW. The third-harmonic distortion is less than 44 dB for input signals up to 500 mV pp. The filter active area is only 900 200 m 2. The supply voltages used are 1.5 V.

Four continuous-time strategies to improve the speed-accuracy-power tradeoff in CMOS amplifiers by using low-power offset-compensation circuits are presented. The offset contribution at the output voltage is extracted and used to modify the DC component of the input voltage or the value of the active load, through low frequency feedback loops, which are realized using two transistors operating in weak inversion and a small capacitor. Because these circuits do not affect the bandwidth and allow using small transistors, the power consumption is greatly reduced with respect to an uncompensated amplifier of the same speed and offset behavior. The proposed strategies present reduced costs in area, power consumption and complexity, and a decrease in the low frequency noise contributions. MonteCarlo, HSPICE simulations results of common source, class AB and fully differential amplifiers, and experimental results of a class AB amplifier, all implemented in a 0.5-lm CMOS technology are shown. Statistical analyses of these strategies are also presented. Improvements up to 99.74% and 398.6% in the offset and the power consumption are respectively observed.

A simple technique to implement highly power efficient class AB-AB Miller op-amps is presented in this paper. It uses a composite input stage with resistive local common mode feedback that provides class AB operation to the input stage and essentially enhances the op-amp's effective transconductance gain, the dc open-loop gain, the gain-bandwidth product, and slew rate with just moderate increase in power dissipation. The experimental results of op-amps in strong inversion and subthreshold fabricated in a 130-nm standard CMOS technology validate the proposed approach. The op-amp has 9 V•pF/µs•µW large-signal figure of merit (FOM) and 17 MHz • pF/µW smallsignal FOM with 1.2-V supply voltage. In subthreshold, the op-amp has 10 V • pF/µs • µW large-signal FOM and 92 MHz • pF/µW small-signal FOM with 0.5-V supply voltage. Index Terms-Analog integrated circuits, class AB-AB Miller op-amps, Miller compensation, resistive local common mode feedback. I. INTRODUCTIONT HE increasing demand for battery-operated portable electronics equipment requires power-efficient analog circuits. The operational amplifier (op-amp) is the essential building block of analog signal processing units [1], [2]. Due to the reduction of the supply voltage in deep submicrometer mixed-signal design, the op-amp may suffer from slew rate limitation, insufficient bandwidth, lower gain, reduced dynamic range, inadequate noise performance, and linearity problems [3]. Hence, the energy-efficient high-speed

No abstract