Low Vccmin fault-tolerant cache with highly predictable performance

Abella, Jaume; Carretero, J. Hernández; Chaparro, Pedro; Vera, Xavier; González, Antonio

doi:10.1145/1669112.1669128

Cited by 75 publications

(90 citation statements)

References 19 publications

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“…Larger cells have a lower probability of failure because non-uniformities in channel doping average out with larger transistors, resulting in more robust devices, but at the price of larger area, and higher energy consumption. Table 1 describes the six SRAM cells of Zhou's study (C1, C2, C3, C4, C5, and C6) with their areas relative to the smallest cell (C1), as well as the percentages of non-faulty entries of a cache implemented with the cells at 0.5 V, assuming 64-byte cache entries 1 . An entry is considered faulty if it contains at least one defective bit.…”

Section: Process Variation In Sram Cellsmentioning

confidence: 99%

“…Word disabling tracks defects at word-level granularity, and then combines two consecutive cache entries into a single fault-free entry, halving both associativity and capacity [39]. Abella et al bypass faulty subentries rather than disabling full cache lines, but this technique is suitable only for the first-level cache, where accesses are word wide [1].…”

Section: Related Workmentioning

confidence: 99%

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Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Ferrerón

Gracia

Alastruey-Benedé

et al. 2016

IEEE Trans. Comput.

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Abstract-Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100% of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression-and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2%, even when using small SRAM cells, which implies over 90% of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.

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Section: Process Variation In Sram Cellsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Ferrerón

Gracia

Alastruey-Benedé

et al. 2016

IEEE Trans. Comput.

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“…Schemes such as Replication Cache [24] and ZerehCache [25] use external spare caches. Similarly, variants of fault-grouping and fault remapping have been used to tolerate faulty cache blocks without adding any spare elements, but by using other parts of the cache, such as GRP2 [26], RDC-Cache [27], Abella [28], Archipelago [29], and FFT-Cache [36]. Wilkerson's scheme [21] also could be considered to fall under this category.…”

Section: Architecture-level Techniquesmentioning

confidence: 99%

Multi-Layer Memory Resiliency

Dutt

Gupta

Nicolau

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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With memories continuing to dominate the area, power, cost and performance of a design, there is a critical need to provision reliable, high-performance memory bandwidth for emerging applications. Memories are susceptible to degradation and failures from a wide range of manufacturing, operational and environmental effects, requiring a multi-layer hardware/software approach that can tolerate, adapt and even opportunistically exploit such effects. The overall memory hierarchy is also highly vulnerable to the adverse effects of variability and operational stress. After reviewing the major memory degradation and failure modes, this paper describes the challenges for dependability across the memory hierarchy, and outlines research efforts to achieve multi-layer memory resilience using a hardware/software approach. Two specific exemplars are used to illustrate multilayer memory resilience: first we describe static and dynamic policies to achieve energy savings in caches using aggressive voltage scaling combined with disabling faulty blocks; and second we show how software characteristics can be exposed to the architecture in order to mitigate the aging of large register files in GPGPUs. These approaches can further benefit from semantic retention of application intent to enhance memory dependability across multiple abstraction levels, including applications, compilers, run-time systems, and hardware platforms.

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“…Other cache disabling methods include cache way disabling, cache set disabling, and sub-block disabling [19,20]. For the cache way disabling technique, full cache ways will be disabled whenever they contain one or several faulty cells; cache set disabling technology disables full cache sets when they contain one or several faulty-cells; sub-block disabling technique only discards the faulty sub-block, while the reset faulty-free sub-block can still be used in the case of faulty cells.…”

Section: Hard Error Management Techniquesmentioning

confidence: 99%

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

Zhang

Ampadu

2014

JLPEA

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Abstract:We propose a novel two-layer error control code, combining error detection capability of rectangular codes and error correction capability of Hamming product codes in an efficient way, in order to increase cache error resilience for many core systems, while maintaining low power, area and latency overhead. Based on the fact of low latency and overhead of rectangular codes and high error control capability of Hamming product codes, two-layer error control codes employ simple rectangular codes for each cache line to detect cache errors, while loading the extra Hamming product code checks bits in the case of error detection; thus enabling reliable large-scale cache operations. Analysis and experiments are conducted to evaluate the cache fault-tolerant capability of various existing solutions and the proposed approach. The results show that the proposed approach can significantly increase Mean-Error-To-Failure (METF) and Mean-Time-To-failure (MTTF) up to 2.8×, reduce storage overhead by over 57%, and increase instruction per-cycle (IPC) up to 7%, compared to complex four-way 4EC5ED; and it increases METF and MTTF up to 133×, reduces storage overhead by over 11%, and achieves a similar IPC compared to simple eight-way single-error correcting double-error detecting (SECDED). The cost of the proposed approach is no more than 4% external memory access overhead.

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Low Vccmin fault-tolerant cache with highly predictable performance

Cited by 75 publications

References 19 publications

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Multi-Layer Memory Resiliency

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

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