Low-temperature LPCVD of Si nanocrystals from disilane and trisilane (Silcore®) embedded in ALD-alumina for non-volatile memory devices

Brunets, I.; Aarnink, Antonius A.I.; Boogaard, A.; Kovalgin, Alexeij Y.; Wolters, R.A.M.; Holleman, J.; Schmitz, Jurriaan

doi:10.1016/j.surfcoat.2007.03.035

Cited by 14 publications

(17 citation statements)

References 22 publications

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“…In our fabrication process, the optically active silicon nanocrystal material is instead obtained by sequential atomic layer deposition (ALD) of 20 nm thick layers of Al 2 O 3 (at 300 °C) and low pressure chemical vapor deposition (LPCVD) of silicon (at 325 °C). This process flow results in smooth and abrupt interfaces and allows precise control of both the insulator layer thickness and the internal locations of nanocrystal layers [4]. Four layers of silicon and five layers of alumina are grown without vacuum break for a total insulator layer thickness of ~100 nm.…”

Section: Device Fabricationmentioning

confidence: 99%

A silicon-based electrical source of surface plasmon polaritons

et al. 2009

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After decades of process scaling driven by Moore's law, the silicon microelectronics world is now defined by length scales that are many times smaller than the dimensions of typical micro-optical components. This size mismatch poses an important challenge for those working to integrate photonics with complementary metal oxide semiconductor (CMOS) electronics technology. One promising solution is to fabricate optical systems at metal/dielectric interfaces, where electromagnetic modes called surface plasmon polaritons (SPPs) offer unique opportunities to confine and control light at length scales below 100 nm (refs 1, 2). Research groups working in the rapidly developing field of plasmonics have now demonstrated many passive components that suggest the potential of SPPs for applications in sensing and optical communication. Recently, active plasmonic devices based on III-V materials and organic materials have been reported. An electrical source of SPPs was recently demonstrated using organic semiconductors by Koller and colleagues. Here we show that a silicon-based electrical source for SPPs can be fabricated using established low-temperature microtechnology processes that are compatible with back-end CMOS technology.

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Section: Device Fabricationmentioning

confidence: 99%

A silicon-based electrical source of surface plasmon polaritons

et al. 2009

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“…Therefore, the use of non‐crystalline Si‐NPs can be advantageous for the long‐term stability of the storage function. The choice of high‐ k dielectrics such as Al 2 O 3 instead of SiO 2 has recently gained attention in NFGM research . As a blocking layer, Al 2 O 3 enables reduction of oxide thickness while maintaining barrier function, which can be used to achieve a better capacitive coupling and therefore a reduction of the operating voltage .…”

Section: Introductionmentioning

confidence: 99%

Integrated low‐temperature process for the fabrication of amorphous Si nanoparticles embedded in Al₂O₃ for non‐volatile memory application

Ilse

Schneider

Ziegler

et al. 2016

Physica Status Solidi (a)

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5589-101A new low-temperature, integrated fabrication process for multi layers of silicon nanoparticles (Si-NPs) embedded in amorphous Al 2 O 3 is presented. For this, a non-thermal low-pressure inductively coupled plasma process (LPICP) for Si-NPs and thermal atomic layer deposition (ALD) of Al 2 O 3 are combined. Storage characteristics of metal-oxidesemiconductor (MOS) structures are studied for non-volatile memory application. The influence of typical fixed oxide charges in Al 2 O 3 on the programming process and retention is investigated.HAADF and EDX images of MOS structure with five layers of silicon nanoparticles.

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“…CMOS front-end CMOS back-end (Al) [20] polymer substrates [22] CMOS back-end (Cu) [19] III-V materials [17] c-Si solar cell [18] PMA [24,25] Si 3 N 4 LPCVD thermal oxidation of silicon TiN ALD [26] Si-ND LPCVD [27] Al 2 O 3 ALD [28] SiO 2 TEOS-LPCVD [23] SiO 2 ICPECVD [29] organic electronics [21] a-Si solar cell [18] …”

Section: Aims Of This Workmentioning

confidence: 99%

“…[ [17][18][19][20][21][22][23][24][25][26][27][28][29] The performance advantages provided by the mentioned process steps are demonstrated using electronic devices realized at CMOS backendcompatible temperatures, i.e. temperatures well below 450 °C.…”

Section: Figure 13: Typical Process Temperatures For State-of-the-armentioning

confidence: 99%

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Electronic devices fabricated at CMOS backend-compatible temperatures

Brunets¹

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Low-temperature LPCVD of Si nanocrystals from disilane and trisilane (Silcore®) embedded in ALD-alumina for non-volatile memory devices

Cited by 14 publications

References 22 publications

A silicon-based electrical source of surface plasmon polaritons

A silicon-based electrical source of surface plasmon polaritons

Integrated low‐temperature process for the fabrication of amorphous Si nanoparticles embedded in Al₂O₃ for non‐volatile memory application

Electronic devices fabricated at CMOS backend-compatible temperatures

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Low-temperature LPCVD of Si nanocrystals from disilane and trisilane (Silcore®) embedded in ALD-alumina for non-volatile memory devices

Cited by 14 publications

References 22 publications

A silicon-based electrical source of surface plasmon polaritons

A silicon-based electrical source of surface plasmon polaritons

Integrated low‐temperature process for the fabrication of amorphous Si nanoparticles embedded in Al2O3 for non‐volatile memory application

Electronic devices fabricated at CMOS backend-compatible temperatures

Contact Info

Product

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Integrated low‐temperature process for the fabrication of amorphous Si nanoparticles embedded in Al₂O₃ for non‐volatile memory application