Low-temperature grown single-crystal Si on <i>epi</i> Ge(001)-2 × 1 and its oxidation: electronic structure study via synchrotron radiation photoemission

Hong

et al. 2021

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Single-crystal silicon (Si) of six monolayer thickness was epitaxially grown on epi-germanium (Ge) in the (001) orientation at substrate temperatures lower than 300 °C, followed by direct deposition of hafnium oxide (HfO2) and aluminum oxide (Al2O3) under ultra-high vacuum. We monitored and studied the Si growth and its epitaxy with the epi-Ge substrate using in-situ reflection high-energy electron diffraction and high-resolution synchrotron radiation X-ray diffraction. Using the gate stacks, we obtained interfacial trap densities of (1–3) × 1011 eV–1 cm–2 without the use of high-pressure hydrogen annealing and a highly reliable Ge p-type metal-oxide semiconductor with a high acceleration factor of 11.

Section: Resultsmentioning

confidence: 85%

Section: ■ Results and Discussionmentioning

confidence: 99%

Low-Temperature-Grown Single-Crystal Si Epitaxially on Ge, Followed by Direct Deposition of High-κ Dielectrics–Attainment of Low Interfacial Traps and Highly Reliable Ge MOS

Hong

et al. 2021

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“…The Ge segregation in the low temperature (<300 °C) MBE-grown epi- Si on Ge , was below the detection limit of X-ray photoelectron spectroscopy (XPS). We employed the SRPES technique with much higher surface sensitivity and resolution than XPS to study the six MLs thick- epi -Si on epi -Ge(001).…”

Section: Resultsmentioning

confidence: 98%

“…Fit to the Ge 3d core-level spectra of (a) the pristine epi -Ge(001)-2×1 . and (b) six MLs of epi -Si on Ge(001), and (c) a fit to the Si 2p core-level spectrum of epi -Si on Ge(001) . [Copyright 2017 & 2020 The Japan Society of Applied Physics.…”

Section: Resultsmentioning

confidence: 99%

“…To minimize the Ge segregation (segGe) and the GeO x formation in the gate dielectrics, a Si layer on Ge using chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) was employed. Compared with the approaches of oxidized Ge and high-κ deposition on Ge, where the formation of GeO x is inevitable, the diffusion of Ge (diff-Ge) into the thin Si layer and segGe on top of the Si surface lessened in the Si-layer approaches, although it still occurred; these were studied by synchrotron radiation photoelectron spectroscopy (SRPES) for the MBE epi -Si/Ge and by secondary-ion mass spectroscopy (SIMS) for the CVD Si/Ge. , A thick Si layer may reduce the segGe but degrades the electron mobility of the devices . In comparison, thin Si of a few monolayers (MLs) produces a smaller conduction band offset between Ge and Si, allowing more electrons to distribute in the Ge channel with higher electron mobility, but causing more segGe in the meantime .…”

Section: Introductionmentioning

confidence: 99%

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Scavenging Segregated Ge on Thin Single-Crystal Si Epitaxially Grown on Ge

Chu

et al. 2021

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Single-crystal Si with six monolayers in thickness was epitaxially grown on epi-Ge(001). The Si surface is characterized with the Ge atoms segregated from the underlying epi-Ge. Some of the Ge atoms bond with the Si inside the film. Upon O2 exposure at room temperature, both the Si and Ge surface atoms are simultaneously oxidized to give rise to four Si charge states and Ge suboxides, respectively. The subsequent in situ annealing at 500 °C under ultra-high vacuum moved the oxygen atom in the Ge suboxides to bond with the nearby Si atom. The annealing also caused the diffused Ge inside the epi-Si to segregate to the surface. The processes of O2 exposure followed by annealing were repeated three times resulting in an oxidized Si/Ge surface having only the four Si oxidized states without GeO x , but with a very small amount of segregated Ge. Using the scavenging process in reducing the segregated Ge prior to the high-κ deposition, the C–V hysteresis of the high-κ/epi-Si/n-Ge(001) metal-oxide-semiconductor (MOS) capacitors decreased more than two times, meaning that the electron traps contributed from the GeO x in the high-κ/epi-Si/Ge(001) are reduced.

High-Ge-Content Si_1–xGe_x Gate Stacks with Low-Temperature Deposited Ultrathin Epitaxial Si: Growth, Structures, Low Interfacial Traps, and Reliability

et al. 2022

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Si1–x Ge x with Ge contents higher than x = 0.5 is expected to boost on-current and improve reliability of p-channel metal-oxide-semiconductor (pMOS) devices. However, unavoidable GeO x formation at the high-κ/Si1‑x Ge x interface with high Ge-contents (HGC) has caused high interfacial trap density, posing a challenge for employing the HGC Si1‑x Ge x as the channel in sub-3 nm complementary MOS technology. In this work, we have deposited epitaxial Si (epi-Si) of six monolayer thickness on Si1–x Ge x at temperatures of 260–280 °C to minimize Ge diffusion and segregation. Si1–x Ge x layers with a wide range of HGC (0.5 < x ≤ 0.8) were grown to investigate the effectiveness of the epi-Si on the Si1–x Ge x . To minimize the GeO x formation caused by the oxidation of the segregated Ge on the epi-Si surface, HfO2 was subsequently deposited via e-beam evaporation on the epi-Si. The measurements using reflection high-energy electron diffraction, high-resolution synchrotron radiation X-ray diffraction, and scanning transmission electron microscopy with high-angle annular-dark-field imaging have revealed the high crystallinity of the epi-Si, the Si1–x Ge x layers, and abrupt interfaces of the high-κ/epi-Si/Si1–x Ge x layers. The well-controlled interfaces have enabled the achievement of low interfacial trap densities (Dit ) of (3–6) × 1011 eV–1 cm–2 in these high-κ/epi-Si/(HGC)Si1–x Ge x samples. The minimum Dit values remained at 3 × 1011 eV–1 cm–2 regardless of the Ge content, confirming the effective passivation of the low-temperature deposited epi-Si. By extracting the effective charge sheet densities for the Si1–x Ge x gate stacks via examination of capacitance–voltage (C–V) hysteresis with decreasing stress voltage in the accumulation region of the MOS capacitors, we have attained very high acceleration factors of 8–12, indicating high reliability of the HfO2/epi-Si/SiGe pMOS gate stacks.