Low-supply-noise low-power embedded modular SRAM

Schultz, K.J.; Gibbins, Robert; Fujimoto, J.S.; Phillips, Ryan S.; Gibson, G.F.R.; Silburt, A.L.

doi:10.1049/ip-cds:19960014

Cited by 8 publications

(2 citation statements)

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“…Another new current-mode 512 x 15 SRAM is also designed. The power-delay product of the new design is 2.02pJ/MHz, which is only 40 percent of that of a recently published design [9].…”

Section: Discussionmentioning

confidence: 67%

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Low-power embedded SRAM macros with current-mode read/write operations

Wang

Yang

Tseng

1998

Proceedings of the 1998 International Symposium on Low Power Electronics and Design - ISLPED '98

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The newly proposed SRAM performs both read and write operations in the current-mode. Due to the current-mode operations, voltage swings at bit-lines and data-lines are kept very small during read and write. The AC power dissipation of bit-lines and data-lines can thus be saved efficiently. For an embedded SRAM macro used in an 8-bit µ-controller, the SRAM using the fully current-mode technique consumes only 30% power dissipation as compared to the SRAM with only currentmode read operation. Experimental results show good agreement with the simulation results and prove the feasibility of the new technique. INTRODUCTIONEmbedded SRAM's are an important dissipation source in many VLSI chips because they contain high-capacitance buses and they are frequently accessed. Several design techniques have been proposed to reduce the power dissipation of SRAM's [1][2]. These techniques are usually used to reduce the active DC current. In the other respect, to obtain a fast read, the cell signal on the bit-line is made as small as possible, transmitted to the common data-line and amplified by a sense amplifier. The small voltage swing on the bit-line also leads to small AC power dissipation consumed by the large bit-line capacitance. Recently, several current-mode sensing circuits [3]-[6] are proposed to overcome the problem of possible speed degradation due to large bit-line and/or data-line capacitances. Current sensing provides the advantage of extremely small bit-line and data-line voltage swings, which also leads to further reduction of AC power dissipation.Above mentioned techniques mainly attempt to reduce the power dissipation during read. The memory cell is usually designed to have enough static noise margin, and thus it needs a near full supply-voltage swing on the bit-line to override the original cell data during write. This large voltage swing will consume a lot of AC power according to the law of CV 2 f . Recently, researches [7] and [8] start to pay attention to the power dissipation during write. In [7], by using a memory cell with different transistor sizes than the conventional one, write can be performed by pulling one of the bit-lines to 1V while the other is 0V. Although the dissipation associated with write operations is reduced, this SRAM design exhibits degraded noise margins compared to the conventional one. While in [8], the theory of energy recovery is applied for the purpose of power reduction during write. However, the design is restricted to the pipelined SRAM and it needs a resonant clock driver, which may not be implemented easily on chip.Besides using some conventional techniques for DC power reduction, a new SRAM design technique, which performs both read and write operations in the current-mode, is proposed in this paper to further reduce the AC power dissipation associated with bit-lines and data-lines. The new technique is adapted from a conventional design [5], which only performs read operation in the current-mode. The new design needs a new memory cell with seven MOS transistors...

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“…Another new current-mode 512 x 15 SRAM is also designed. The power-delay product of the new design is 2.02pJ/MHz, which is only 40 percent of that of a recently published design [9].…”

Section: Discussionmentioning

confidence: 67%

“…In 1996, K. J. Schultz et al published a paper [9] to demonstrate a very-low power 512 x 15 embedded synchronous SRAM using the technique of divided wordline. For comparison, a new current-mode 512 x 15 SRAM was also designed and simulated.…”

Section: X 15 Sram'smentioning

confidence: 99%