Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications

Chiu, Pi-Feng; Chang, Meng‐Fan; Wu, Che-Wei; Chuang, Ching-Hao; Sheu, Shyh-Shyuan; Chen, Yu‐Sheng; Tsai, Ming-Jinn

doi:10.1109/jssc.2012.2192661

Cited by 141 publications

(56 citation statements)

References 34 publications

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“…To prevent floating lines from creating paths between VDD and VSS at the inputs of sub blocks or units to which they are connected, isolation gates are inserted to force these lines to low. Isolation logic is implemented by means of AND cells because of their input circuit structure which allows floating one or more inputs while at least one input is forced to a low state [6,7]. In the 2-input AND circuit, a low state at isolation control input B opens the transistor T4 and closes T2; as a consequence, voltage at node N1 which drives the inverting output stage is tied to VDD regardless of the states of T1 and T3 thus forcing output Z to a low state.…”

Section: Isolation Logicmentioning

confidence: 99%

Optimization of SRAM in 28nm HPM Technology

Zhou¹,

Xing²,

Zhang³

2018

Proceedings of the 2018 Joint International Advanced Engineering and Technology Research Conference (JIAET 2018)

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Abstract. This paper presents an optimized SRAM that is repairable and consumes less power dissipation. To increase the percent of good SRAMs per wafer, redundancy logic and e-fuse box are added to SRAM, thereby building SR SRAM. In order to reduce power dissipation, power on/off states and isolation logic are introduced to SR SRAM, consequently constructing LPSR SRAM. Also the testing methodology of the SoC which has been successfully implemented Chartered 28nm HPM process is discussed. The testing results indicate that 25% of power saving is obtained to the LPSR SRAM64K×32 and the percent of the good LPSR SRAM64K×32s per wafer is increased by 20%.

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Section: Isolation Logicmentioning

confidence: 99%

Optimization of SRAM in 28nm HPM Technology

Zhou¹,

Xing²,

Zhang³

2018

Proceedings of the 2018 Joint International Advanced Engineering and Technology Research Conference (JIAET 2018)

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“…In [92], The authors introduced a study of a memristor-based nonvolatile SRAM (or memristor latch) cell to achieve fast bit-to-bit parallel store/restore operations, low store/restore energy consumption, and a compact cell area which is suitable for low power mobile applications. This memristive nonvolatile 8T2R (Rnv8T) cell includes two fast-write memristor (RRAM) devices vertically stacked over the 8T, and a novel 2T memristor switch, which provides both memristor control and SRAM write-assist functions.…”

Section: Memroriesmentioning

confidence: 99%

Memristor: Models, Types, and Applications

Radwan

Fouda

2015

Studies in Systems, Decision and Control

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The first concept and realization of memory resistor device was proposed by Widrow in 1960 [1]. It was named memistor and had three terminals. The resistance of this memistor was variable and could be controlled and sensed using the control (DC current) and sensing (AC current) terminals. The significant difference between the transistor and the memistor is that the memistor resistance is controlled by the instantaneous time integral of the control current, which is the accumulated charge passing through the memistor. However, the memistor was not linked to the fundamentals of circuit theory because it is an "ill-posed" element, a 3-terminal device is said to be well posed if it has sufficient information to predict the current and voltage associated with all the three terminals when the device is connected to an arbitrary external circuit [2]. Moreover, in 1968, through the Electromagnetic theory, Fano et al. listed that there are four fundamental circuit elements: resistor, capacitor, inductor, and an unknown element [3].However, the first practical mathematical concept and realization was introduced by the father of nonlinear circuits, Prof. Leon Chua, in 1971 in his seminal paper

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“…The proposed SRAM cell has power delay products of 0.6371eÀ18 and 0.5721eÀ19 for write and read operations, respectively. The same table [14] 6.822 9.201 7T [15] 6.323 10.451 Sub threshold 7T [16] 10.033 14.611 8T [17] 11.432 15.402 Vertical stacked 8T [18] 10.663 15.011 9T [19] 12.644 16.633 9T in sub threshold region [20] 14.669 17.821 Single ended 9T [21] 11.421 13.442 Fully differential 10T [22] 9.754 12.877 PNP based differential 10T [23] 12.540 15.429 11T [24] 15 shows that even the access time of the proposed SRAM cell is high but the power delay product is lesser because of more reduction in total power dissipation as compared with the other existing SRAM cells. So from the above results it is evident that the 12T proposed SRAM cell can provide better power solution than the other existing SRAM cells for portable devices if area of the device is not of prime concern.…”

Section: Power Delay Productmentioning

confidence: 99%

“…So from the above results it is evident that the 12T proposed SRAM cell can provide better power solution than the other existing SRAM cells for portable devices if area of the device is not of prime concern. [14] 6.294 9.257 7T [15] 7.197 10.013 Sub threshold 7T [16] 4.913 6.790 8T [17] 7.315 9.157 Vertical stacked 8T [18] 5.223 7.331 9T [19] 8.371 10.226 9T in sub threshold region [20] 4.280 7.016 Single ended 9T [21] 5.821 7.433 Fully differential 10T [22] 4.852 6.291 PNP based differential 10T [23] 4.374 6.195 11T [24] 3.893 5.033…”

Section: Power Delay Productmentioning

confidence: 99%