Low standby power charge trap flash memory with tunneling field effect transistor

Han, Min; Lee, Jong Ho; Seo, Dongsun; Park, Chong-Dae; Oh, Young-Cheol; Cho, Il Hwan

doi:10.1109/snw.2012.6243349

Cited by 5 publications

(7 citation statements)

References 5 publications

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“…The detailed operation scheme was introduced in our previous work. 16) As shown in Fig. 2, the program disturbance occurs in neighboring cells, which share the same word line with the selected cell.…”

Section: Resultsmentioning

confidence: 99%

“…23) In this paper, the program inhibition method is based on the reduction in the number of electron carriers in the channel region, as suggested but not analyzed in our previous work. 16) Figure 4(a) shows the threshold voltage shift and tunneling barrier width variation of selected and unselected cells when the memory array is operated with the suggested program scheme. In this analysis, the threshold voltage is measured with the constant current method at I d = 10 ¹7 A/µm.…”

Section: Resultsmentioning

confidence: 99%

“…In a previous work, the unit memory cell characteristics of the flash memory with TFET and array structure were introduced by our group. 16) The operation characteristics of the unit memory cell such as program and erase characteristics were extensively investigated, and the memory array operation scheme was also suggested through the previous work. 16) In the previous work, the flash memory with TFET used Fowler-Nordheim (FN) program methods for low power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…16) The operation characteristics of the unit memory cell such as program and erase characteristics were extensively investigated, and the memory array operation scheme was also suggested through the previous work. 16) In the previous work, the flash memory with TFET used Fowler-Nordheim (FN) program methods for low power consumption. However, the disturbance characteristics of the flash memory with TFET were not sufficiently investigated.…”

Section: Introductionmentioning

confidence: 99%

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Disturbance characteristics of charge trap flash memory with tunneling field-effect transistor

Cho

Choi

et al. 2014

Jpn. J. Appl. Phys.

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In this study, the disturbance characteristics of silicon–oxide–nitride–oxide–silicon (SONOS) memory based on the tunneling field-effect transistor (TFET) are investigated in terms of the Fowler–Nordheim (FN) program. Since the TFET SONOS memory uses a depletion channel region for program inhibition, the tunneling of an inhibited cell considers both the electron concentration and the vertical electric field. The effects of both parameters on tunneling current are analyzed using device simulation and the tunneling current equation. The tunneling current of the source-side region depends on the electric field and that of the drain-side region depends on the electron concentration. These results can be applied to the performance optimization of the TFET SONOS memory.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Disturbance characteristics of charge trap flash memory with tunneling field-effect transistor

Cho

Choi

et al. 2014

Jpn. J. Appl. Phys.

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“…Moreover, the performance of tunneling‐based transistors can further be improved through material 18–23 and device 13 engineering. Besides, experimental demonstration of tunneling‐based long‐channel SONOS ( T ‐SONOS) memory cell has been previously reported by the authors in References 24–31.…”

Section: Introductionmentioning

confidence: 97%

Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell

Bohara

Vishvakarma

2021

Int J Numerical Modelling

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This work reports on the triple‐level NAND flash cell realized from self‐amplified (SA) double gate (DG) tunneling‐based silicon‐oxide‐nitride‐oxide‐silicon (T‐SONOS) memory device. Through calibrated simulations, we show that capacitive coupling between the front gate and back gate can be used to store eight states (or 3 bits), that is, from “000” to “111,” in a T‐SONOS memory device with the readable difference between each level at lower programming voltages. The performance of the multilevel T‐SONOS cell is compared with the inversion mode SONOS (I‐SONOS) multilevel cell. Results highlight that gate length (Lg) scaling from 100 to 25 nm significantly deteriorates the threshold voltage associated with the lower states in the I‐SONOS multilevel cell. However, highly stable eight states can be achieved in a multi‐level T‐SONOS cell at Lg = 25 nm. The results highlight the potential of SA T‐SONOS cell for designing multilevel memory cell arrays.

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Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

Cao

Tian

Majumdar

et al. 2021

Semicond. Sci. Technol.

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A novel vertical tunnelling field-effect transistor (TFET) based on silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device, named as VT-SONOS, is proposed and investigated using TCAD simulations. Different from traditional planar TFET-based SONOS memory, the VT-SONOS device is programmed via band-to-band tunnelling for vertical pocket and Fowler–Nordheim tunnelling for both pocket/bottom oxide (OXb) and channel/OXb regions, which leads to a steeper subthreshold swing (SS) and a larger on-state current (I ON). The device structure is constructed using Sentaurus TCAD tools, and I D–V G characteristics were extracted using TCAD tools. Obtained SS value is 102.09 mV dec−1, while the I ON was 3.02 × 10−4 A. The memory window was 2.95 V, showing more dependence on programming pulse height (V gp) than erasing pulse height (V ge). Furthermore, 10-year retention characteristics were studied to investigate critical reliability issue. About 60% of the initial trapped charges remained in the device after unbiased 3.15 × 108 s (10 years) storage.

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Low standby power charge trap flash memory with tunneling field effect transistor

Cited by 5 publications

References 5 publications

Disturbance characteristics of charge trap flash memory with tunneling field-effect transistor

Disturbance characteristics of charge trap flash memory with tunneling field-effect transistor

Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell

Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

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