Low resistivity α-tantalum in Cu/CVD low-k (Orion™) integration

Donohue, H.; Yeoh, J. C.; Giles, K.; Buchanan, Keith

doi:10.1016/s0167-9317(02)00802-x

Cited by 14 publications

(9 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Which crystal structure forms depends significantly on processing conditions. While most PVD processes lead to β-Ta films, especially when the film is deposited onto a dielectric material, careful adjustments of processing parameters as well as the use of a TaN underlayer or a CVD process were observed to produce the low resistivity α-Ta [Edelstein 2001, Donohue 2002, Hecker 2002, Demuynck 2003]. Different crystal structures within one film were found as well [Lee 1999, Kwon 2000.…”

Section: Simulation Of Resistance-based Void Sizesmentioning

confidence: 99%

Statistical Analysis of Electromigration Lifetimes and Void Evolution for Cu Interconnects

Hauschildt

Gall²,

Thrasher³

et al. 2004

MRS Proc.

View full text Add to dashboard Cite

Electromigration (EM) failure statistics and the origin of the lognormal deviation (σ) for Cu interconnects have been investigated by analyzing the lifetime statistics and void size distributions at various stages during EM testing. Experiments were performed on 0.18 μm wide Cu interconnects with tests terminated after specific amounts of resistance increases, or after a specified test time. Void size distributions of resistance-based, as well as time-based EM tests were obtained using focused ion beam (FIB) microscopy. The lifetime and void size distributions were found to follow lognormal distribution functions. The σ values of EM lifetime and time-based void size distributions decrease with higher percentages of resistance increase, reaching an asymptotic value of σ ∼ 0.14. In contrast, σ values of resistance-based void size distributions are significantly smaller and do not show an obvious dependence on time. The statistics of resistance-based void size distributions can mainly be accounted for by geometrical variations of the void shape, while the statistics of time-based void size distributions requires consideration of kinetic aspects of the EM process. The σ values of EM lifetime distributions at long times can be simulated based on measured void size distributions, taking into account geometrical and experimental factors of EM. In contrast, for short times the statistics of initial void formation and the kinetics of interfacial mass transport have to be considered.

show abstract

Section: Simulation Of Resistance-based Void Sizesmentioning

confidence: 99%

Statistical Analysis of Electromigration Lifetimes and Void Evolution for Cu Interconnects

Hauschildt

Gall²,

Thrasher³

et al. 2004

MRS Proc.

View full text Add to dashboard Cite

show abstract

“…It is reported that when Ta is sputtered on a TaN substrate, the a phase is formed with a preferential (1 1 0) texture [25,26]. When Ta is sputtered on SiO 2 , the b-phase of tantalum is readily formed and exhibits a (0 0 2) preferred orientation perpendicular to the film surface [27,28]. Fig.…”

Section: Discussionmentioning

confidence: 99%

Surface diffusion of copper on tantalum substrates by Ostwald ripening

2007

View full text Add to dashboard Cite

“…The RS device fabrication started with a 300 mm diameter Si (001) substrate coated with a 100 nm thick thermal oxide. A standard Ta/TaN adhesion layer followed by Cu seed layer were then deposited on the oxide using industry standard physical vapor deposition (PVD) methods [58,59]. An electrochemical plating method was then utilized to grow a thick Cu film that was subsequently thinned to approximately 300 nm in thickness via chemical mechanical polishing [60,61].…”

Section: Device Fabricationmentioning

confidence: 99%

Characterization of Porous BEOL Dielectrics for Resistive Switching

King

Bielefeld

et al. 2016

ECS Trans.

View full text Add to dashboard Cite

Porous back-end dielectric materials with porosity ranging from 8% to 25% have been characterized in terms of their resistive switching behavior. The porous dielectric is sandwiched between Cu and W or Pt electrodes. Some metal-insulator-metal structures have a 2 nm SiCN diffusion barrier at either electrode or at both electrodes. 90% of samples are intrinsically conductive due to strong Cu doping of the dielectric. About 10% of the samples display resistive switching behavior, of which devices with two SiCN barriers can be switched repeatedly, demonstrating that resistive switching in porous dielectrics is feasible. The forming voltage of the filaments increases with increasing porosity of the dielectric. Depending on the voltage polarity, Cu and oxygen vacancy conductive filaments can be formed. The properties of resistive switching established in this work provide a solid basis for further improvement of ReRAM devices based on porous dielectrics compatible with CMOS backend.

show abstract

Low resistivity α-tantalum in Cu/CVD low-k (Orion™) integration

Cited by 14 publications

References 5 publications

Statistical Analysis of Electromigration Lifetimes and Void Evolution for Cu Interconnects

Statistical Analysis of Electromigration Lifetimes and Void Evolution for Cu Interconnects

Surface diffusion of copper on tantalum substrates by Ostwald ripening

Characterization of Porous BEOL Dielectrics for Resistive Switching

Contact Info

Product

Resources

About