Low power test pattern generator for BIST

Puczko, M.

doi:10.1109/wzee.2015.7394030

Cited by 5 publications

(2 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It focuses on at-speed testing, power efficiency through multi-voltage design, and area cost reduction, with successful tool implementation demonstrated in Xilinx ISE and Design Compiler. These studies underscore a shift towards more efficient, flexible, and power-conserving testing methodologies in semiconductor design [17][18][19][20].…”

Section: Literature Reviewmentioning

confidence: 99%

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Ramakrishna S , Rajashekhar B Shettar

2024

jes

View full text Add to dashboard Cite

This paper presents a novel approach to optimizing power usage in scalable Built-In Self-Test (BIST) controllers. While BIST mechanisms are crucial for maintaining the reliability of digital circuits, they can be excessively power-hungry during testing phases, particularly in applications where energy consumption is a concern. We propose an innovative architecture incorporating reversible logic gates and circuits to overcome this challenge. Reversible logic is renowned for its low power consumption as it retains information. By integrating reversible logic into our architecture, we can significantly reduce power usage during test cycles, making it an ideal solution for scalable systems ranging from 8 to 32 bits. Our trials showed substantial power savings compared to traditional BIST approaches without sacrificing test coverage or efficiency. Our research provides new opportunities to develop energy-efficient testing methods for digital circuits, contributing to broader efforts in sustainable electronics design.

show abstract

Section: Literature Reviewmentioning

confidence: 99%

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Ramakrishna S , Rajashekhar B Shettar

2024

jes

View full text Add to dashboard Cite

show abstract

“…Nowadays VLSI testing is always used to ensure the correctness and reliability of the finished chip [1], but we encountered some problems during VLSI testing. In the process of chip testing, the test power consumption is two to four times greater compared with the normal power consumption [2,3]. This excessive power consumption will limit the stability of the circuit and it will also increase the cost of packaging [4].…”

Section: Introductionmentioning

confidence: 99%

Low Cost Test Pattern Generation in Scan-Based BIST Schemes

et al. 2019

View full text Add to dashboard Cite

This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.

show abstract