Low Cost Test Pattern Generation in Scan-Based BIST Schemes

Zhang, Guohe; Yuan, Ye; Liang, Feng; Wei, Sufen; Yang, Cheng-Fu

doi:10.3390/electronics8030314

Cited by 7 publications

(2 citation statements)

References 19 publications

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“…Zhang et al reported "Low Cost Test Pattern Generation in Scan-Based BIST Schemes" [12]. This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes.…”

Section: The Topics Of Intelligent Electronic Device and Its Applicatmentioning

confidence: 99%

Special Issue on Intelligent Electronic Devices

2020

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The second IEEE International Conference on Knowledge Innovation and Invention 2019 (IEEE ICKII 2019) was held in Seoul, South Korea, 12–15 July 2019. This special issue “Intelligent Electronic Devices” selects 13 excellent papers form 260 papers presented in IEEE ICKII 2019 conference about the topics of Intelligent Electronic Devices. The main goals of this special issue are to encourage scientists to publish their experimental and theoretical results in as much detail as possible, and to discover new scientific knowledge relevant to the topics of electronics.

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Section: The Topics Of Intelligent Electronic Device and Its Applicatmentioning

confidence: 99%

Special Issue on Intelligent Electronic Devices

2020

Self Cite

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“…Furthermore, the memories are more prone to faults than the actual logic, as memories do not consist of the logic elements such as flip-flops [ 3 , 4 ], and the defects in the embedded memory of the devices or the systems can cause a critical error. Therefore, regress testing embedded memories in today’s complex SoC-based systems becomes necessary to retain the products’ reputation in the market.…”

Section: Introductionmentioning

confidence: 99%

Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Alnatheer

Ahmed

2021

Micromachines

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The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.

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