Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Alnatheer, Suleman; Ahmed, Mohammed Altaf

doi:10.3390/mi12070811

Cited by 4 publications

(4 citation statements)

References 22 publications

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“…The FPGA performance of the DQL-BSLFSR-FD method is likened to existing approaches. The proposed method's FPGA performance is compared with the memory BIST with optimized BISR for fault detection (FPGA-MBIST-OBISR-FD) [22], SRAM-based Physically Unclonable Function (PUF) with Hot Carrier Injection (HCI) for fault detection (FPGA-PUF-HCI-FD) [23], and the Essential Spare Pivoting (ESP) based Local Repair Most (LRM) (FPGA-ESP-LRM-FD) [27], respectively.…”

Section: Resultsmentioning

confidence: 99%

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Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Ahmed

Alnatheer

2022

Micromachines

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Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-in Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-in Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.

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Section: Resultsmentioning

confidence: 99%

“…However, it does not reduce the power consumption, area, and time while implementing FPGA [20]. A simple BIST and BISR method is presented in the research [21,22]. It uses an MBIST controller and BISR algorithm for testing memory and is implemented on ASIC, and the March algorithm is used in the research to test the MUT.…”

Section: Introductionmentioning

confidence: 99%

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Ahmed

Alnatheer

2022

Micromachines

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“…The results that integrating a MAC unit with SoC increases the area to just 0.0011%. Some SoC-based systems are available in the research study [36][37][38][39][40] for our notice.…”

Section: Resultsmentioning

confidence: 99%

A Smart Memory Controller for System on Chip‐Based Devices

Ahmed

Aloufi

2022

Journal of Nanomaterials

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This research paper deals with a system-on-chip (SoC) architecture design where multiple processors are inbuilt with other blocks of memory and control logic developed by nanomaterials. The multiprocessing-based SoC architecture is commonly used in the latest electronic devices such as smartphones, tablets, and smart wristwatches with large memory sizes. The data handing in these highly memory-dense devices is a critical task, and it needs special attention for the smooth operation of the device. This research proposed a smart controller to exchange data between various processors and input-output devices to tackle this challenge. A proposed controller block controls the data flow between memory and different SoC components and processors. A memory access controller (MAC) is presented in this research study to manage and accelerate data transmission speed and reduce the processors’ activity for SoC-based devices. The proposed MAC will integrate into the SoC with multiprocessing units, including gaming processors, at minimum hardware overhead and low power consumption. It improves the memory accessing efficiency and reduces the processors’ activity of a system. As a result, the system’s performance and power consumption improve at an acceptable level compared with the other conventional methods. This research is aimed at enhancing the performance of any SoC-based device where multiprocessing engines are inbuilt and flexible enough to serve various SoCs.

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“…Analysis time efficient [10], [28], [53], [54] 4 Area overhead and repair rate efficient [25], [27], [36], [63] 5…”

Section: Comparison Of Repair Algorithm Efficiencymentioning

confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories.

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Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Cited by 4 publications

References 22 publications

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

A Smart Memory Controller for System on Chip‐Based Devices

Memory built-in self-repair and correction for improving yield: a review

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