Low-Power, Subthreshold Reference Circuits for the Space Environment: Evaluated with γ-rays, X-rays, Protons and Heavy Ions

Abstract

The radiation tolerance of subthreshold reference circuits for space microelectronics is presented. The assessment is supported by measured results of total ionization dose and single event transient radiation-induced effects under γ -rays, X-rays, protons and heavy ions (silicon, krypton and xenon). A high total irradiation dose with different radiation sources was used to evaluate the proposed topologies for a wide range of applications operating in harsh environments similar to the space environment. The proposed custom designed integrated circuits (IC) circuits utilize only CMOS transistors, operating in the subthreshold regime, and poly-silicon resistors without using any external components such as compensation capacitors. The circuits are radiation hardened by design (RHBD) and they were fabricated using TowerJazz Semiconductor’s 0.18 μm standard CMOS technology. The proposed voltage references are shown to be suitable for high-precision and low-power space applications. It is demonstrated that radiation hardened microelectronics operating in subthreshold regime are promising candidates for significantly reducing the size and cost of space missions due to reduced energy requirements.

Radiation Tolerant Electronics

“…Two samples were irradiated and were able to reach a dose of 2.2 MGy before failing to meet specification due to an increased non-linearity error, originating from the increased mismatch in the charge-pump of the sampling circuit. A comprehensive evaluation of two subthreshold voltage reference circuits with respect to their resilience to SEE, TID, and TID/DD was performed in [6]. The evaluation was supported by measured results with γ-rays, x-rays, protons, and heavy ions.…”

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

“…The choice of the N-channel input transistor relies on the lower thermal noise compared to the P-type at high frequency [ 9 , 18 ], since the 1/f noise is negligible in the frequency region above 10 kHz [ 6 , 38 , 39 ]. In addition, N-channel MOS, gives a lower series white noise with respect to the P-channel counterpart, because of its higher transconductance [ 6 , 27 , 38 ] at the same drain current compared to the PMOS device. The current source at M 1 ’s drain is provided by M 2 , which is a P-channel MOSFET with smaller transconductance.…”

“…The reduction of threshold voltage shift (Vth variations) leads to minimizing the gate-oxide thickness (t ox ) [ 9 , 26 ], then increasing the probability of quantum tunneling of electrons, which enables, therefore, most of the trapped holes caused by induced radiation to be recombined with electrons [ 26 ]. The low-threshold voltage (LVT) operation of subthreshold circuits applies lower electric fields across the gate-oxide [ 27 ]. This will reduce the rate of electron-hole separation and increase the probability of recombination.…”

“…Therefore, a good choice in the pulse shaping parameters is crucial for achieving good energy resolution and minimum pulse pile-up for high counting rates [ 11 , 30 , 31 ]. For high throughput experiments, short shaping time ( ) reduces the pile-up effects and for an optimal design solution, the minimum limits the charge collection process and increases the energy resolution accordingly [ 4 , 12 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 ]. Therefore, it is necessary to propose an optimal front-end circuit to avoid unnecessary power dissipation and heat in closely packed pixel arrays first avoid.…”

A Single-event Transient Mitigation Technique for Bandgap Reference Utilizing in Space Application

“…The related research on the single-event transient (SET) effects of the bandgap reference circuit were reported in [3][4][5][6][7]. The circuitlevel radiation-hardened-by-design (RHBD) techniques, such as the guard ring technique [3], the triode reverse connection [4], and the inverse-mode transistors [5], were adopted in SiGe BiCMOS technology. The suppression of SET pulses was also realized by pulse quenching [6] and DC signal isolation [7] in bulk CMOS process.…”