Low-power SRAMs power mode control logic: Failure analysis and test solutions

Zordan, Leonardo B.; Bosio, Alberto; Dilillo, Luigi; Girard, Patrick; Todri, A.; Virazel, Arnaud; Badereddine, N.

doi:10.1109/test.2012.6401578

Cited by 7 publications

(5 citation statements)

References 15 publications

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“…Secondly, the SRAM must be switched back to ACT mode, which is referred to as wake-up phase, and finally a read operation must be executed in all core-cells to verify if data previously stored have been retained in DS mode. It is an extended version of March LZ [13], which has been proposed to detect faulty behaviors induced by malfunctions of peripheral circuitry power gating. In March m-LZ, notation DSM represents the operation of switching from ACT to DS mode, whereas notation WUP refers to the wake-up phase.…”

Section: Defects That Cause Both Increased Static Power Consumption A...mentioning

confidence: 99%

“…The r 1 operation in ME4 verifies if logic '1' has been retained in all core-cells during the period of time when the SRAM was in DS mode. Operations w 0 and r 0 in ME4 refer to the sensitization and detection of faulty behaviors associated to peripheral circuitry power gating [13]. When the execution of ME4 finishes, all core-cells are expected to hold logic '0'.…”

Section: Defects That Cause Both Increased Static Power Consumption A...mentioning

confidence: 99%

“…Hence, malfunctions of the voltage regulator can lead to data retention faults in low-power SRAMs. Although many works have been done in the area of memory test, notably [9][10][11], only few publications target test of low power SRAMs [12][13].…”

Section: Introductionmentioning

confidence: 99%

“…The PSs of both core-cell array and peripheral circuitry are implemented through a network of PMOS transistors structured in N segments (refer to [12][13] for details). Such PSs, along with a voltage regulation system, enable power modes on the SRAM by varying the supply voltage applied to the core-cell array and peripheral circuitry internal supply lines (V DD _CC and V DD _PC in Fig.…”

Section: Introductionmentioning

confidence: 99%

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Test Solution for Data Retention Faults in Low-Power SRAMs

Zordan

Bosio

Dilillo

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cells as low as possible without data loss. Thus, faulty-free behavior of the voltage regulator is crucial for ensuring data retention in core-cells when the SRAM is in low-power mode. This paper investigates the root cause of data retention faults due to voltage regulator malfunctions. This analysis is done under realistic conditions (i.e., industrial core-cells affected by process variations). Based on this analysis, we propose an efficient test flow for detecting data retention faults in low-power SRAMs.

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Section: Defects That Cause Both Increased Static Power Consumption A...mentioning

confidence: 99%

Section: Defects That Cause Both Increased Static Power Consumption A...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Test Solution for Data Retention Faults in Low-Power SRAMs

Zordan

Bosio

Dilillo

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

View full text Add to dashboard Cite

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“…PSs of core-cell array and peripheral circuitry are implemented through a network of PMOS transistors structured in N segments CSeg i and PSeg i , respectively, i ϵ [0, N -1]. Details have been presented in [10].…”

Section: Introductionmentioning

confidence: 99%

A built-in scheme for testing and repairing voltage regulators of low-power srams

Zordan

Bosio

Dilillo

et al. 2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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Voltage regulation systems offer an efficient mechanism for reducing static power consumption of SRAMs. When the SRAM is not accessed for a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cell array as low as possible without data loss. Therefore, reliable operation of such device must be ensured by using adequate test techniques. In this work, we propose low area overhead built-in self-test (BIST) and built-in self-repair (BISR) schemes that can be embedded on the SRAM to automatically test and repair the voltage regulator. Simulation results prove the effectiveness of the proposed technique for detecting, diagnosing and repairing voltage regulators of low-power SRAMs.Index Terms-SRAM, low-power design, design for testability, memory test.

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