Low-power selective pattern compression for scan-based test applications

Sivanantham, S.; Mallick, P. S.; Perinbam, J. Raja Paul

doi:10.1016/j.compeleceng.2013.11.028

Cited by 8 publications

(6 citation statements)

References 42 publications

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“…Optimum don't care filling and vector reordering approaches have been successfully used to reduce the test power. Alternative Statistical Run Length (ASRL) (Haiying Y. et al 2016) and Low Power Switched Capacitor (LPSC) (Sivanantham S. et al, 2014b), Variablelength input Huffman coding (VIHC) (Gonciari et al 2002), Alternating frequency-directed equal-run-length (AFDER) and runlength based Huffman coding (RLHC) (Sivanantham et al 2014) techniques are examples of approaches that help in achieving a reduction in the test power in addition to test data compression.…”

Section: Analysis Of Existing Literaturementioning

confidence: 99%

An innovative two-stage data compression scheme using adaptive block merging technique

2020

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Test data has increased enormously owing to the rising on-chip complexity of integrated circuits. It further increases the test data transportation time and tester memory. The non-correlated test bits increase the issue of the test power. This paper presents a two-stage block merging based test data minimization scheme which reduces the test bits, test time and test power. A test data is partitioned into blocks of fixed sizes which are compressed using two-stage encoding technique. In stage one, successive blocks are merged to retain a representative block. In stage two, the retained pattern block is further encoding based on the existence of ten different subcases between the sub-block formed by splitting the retained pattern block into two halves. Noncompatible blocks are also split into two sub-blocks and tried for encoded using lesser bits. Decompression architecture to retrieve the original test data is presented. Simulation results obtained corresponding to different ISCAS'89 benchmarks circuits reflect its effectiveness in achieving better compression.

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Section: Analysis Of Existing Literaturementioning

confidence: 99%

An innovative two-stage data compression scheme using adaptive block merging technique

2020

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“…The AERL filling algorithm focuses on maximizing the runs with equal run-length to achieve better compression ratio as well as fewer transitions to reduce test power. The process of filling the X-bits in the test cube with AERL-filling is demonstrated in Fig 1. The weighted transition metric (WTM) is used for measuring scan power transitions as described in [34]. A transition occurs if any two bits are different, i.e.…”

Section: ) Fill All X-bits Between Startpos and Midpos With T And MImentioning

confidence: 99%

“…The compression methods such as alternating FDR (ARL) coding [22], extended FDR (EFDR) coding [21,32], alternating variablelength (AVR) coding [24], equal-run-length coding (ERLC) [22], alternating frequency-directed equal-run-length coding (AFDER) [33], low-power selective pattern compression (LP-SPC), [34] and Shifted Alternating FDR coding [35] consider both runs of 0s as well as 1s to form the codewords. The ARL code [22] is also a variable-to-variable length code.…”

Section: Introductionmentioning

confidence: 99%

“…Several Huffman based compression techniques such as variable-input Huffman coding, variable-to-variable Huffman coding, optimal selective Huffman coding, complementary Huffman coding and run-length based Huffman coding (RLHC) available to improve the compression efficiency, area overhead and the test application time [37]. Many low-power compression techniques are available in the literature for the minimization of test power, test data volume and test time [8,[33][34][35]. In observation-oriented test pattern generation with the scan-chain disabling technique, the test pattern generation process is assisted by testability analysis to generate the observation-oriented test patterns.…”

Section: Introductionmentioning

confidence: 99%

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Test Data Compression with Alternating Equal-Run-Length Coding

Sivanantham¹,

S²,

Ramki³

et al. 2018

IJET

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This paper presents a new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing. The proposed encoding technique focuses on replacing redundant runs of the equal-run-length vector with a shorter codeword. The effectiveness of this compression method depends on a number of repeated runs occur in the fully specified test set. In order to maximize the repeated runs with equal run length, the unspecified bits in the test cubes are filled with the proposed technique called alternating equal-run-length (AERL) filling. The resultant test data are compressed using the proposed alternating equal-run-length coding to reduce the test data volume. Efficient decompression architecture is also presented to decode the original data with lesser area overhead and power. Experimental results obtained from larger ISCAS'89 benchmark circuits show the efficiency of the proposed work. The AERL achieves up to 82.05 % of compression ratio as well as up to 39.81% and 93.20 % of peak and average-power transitions in scan-in mode during IC testing.

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“…Generally, test data volumes can be reduced through three test compression techniques including linear decompression based scheme, broadcast scanbased scheme and code based scheme [13], which are directly applied to current test patterns and avoid any ATPG or fault simulation [15]. Among them, the code based scheme doesn't require circuit structural information and it is suitable for intellectual property cores, so it is preferred in test data compression.…”

Section: Introductionmentioning

confidence: 99%

A Power Efficient BIST TPG Method on Don’t Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering

et al. 2015

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A power efficient BIST TPG method is proposed to reduce test power dissipation during scan testing. Before the test patterns are injected into scan chain, the test set adopts a series of preprocessed strategies including don't care bit based 2-D adjusting, Hamming Distance based 2-D reordering and test cube matrix based two transpose, all steps will be orderly executed in interspersed way. The six largest ISCAS'89 benchmark circuits verify the proposed method. Experimental results show that the switching activities are effectively reduced when the test set is loaded for on-chip scan testing. ASDFR with MT-filling scheme ensures high compression ratio, the scan-in test power dissipation is further decreased by don't care bit based 2-D adjusting and Hamming Distance 2-D reordering. In addition, the BIST TPG method with less test application time and smaller algorithm complexity can be widely applied to actual chip design without adding extra decoder area overhead.

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Low-power selective pattern compression for scan-based test applications

Cited by 8 publications

References 42 publications

An innovative two-stage data compression scheme using adaptive block merging technique

An innovative two-stage data compression scheme using adaptive block merging technique

Test Data Compression with Alternating Equal-Run-Length Coding

A Power Efficient BIST TPG Method on Don’t Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering

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