Low-power network-on-chip for high-performance SoC design

Abstract

An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-onchip (SoC) design. It incorporates heterogeneous intellectual properties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IPs, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Various low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 5 mm 2 chip containing all the above features is fabricated by 0.18-m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW.

A new physical routing approach for robust bundled signaling on NoC links

“…Even if it may theoretically be possible to achieve perfect delay matching for irregularly routed links, this would imply numerous design convergence iterations (which take days for an average size SoC). Moreover, high-performance NoC implementation often relies on low-swing signaling to boost energy efficiency [22,23,27]. Signal-to-noise ratio is a serious concern in both low-swing and full-swing communication [26,27].…”

Baseband Analog Circuits for Software Defined Radio

“…Digital knobs are introduced in analog components making them switchable and, therefore, programmable at a software level by means of a fast digital interface. In this context, a number of recent research studies (Kangmin et al, 2006;Srinivasan et al, 2006) have demonstrated the feasibility and advantages of Network-on-Chip (NoC) over traditional bus-based architectures. 3.…”

Serialized Asynchronous Links for NoC

“…The benefit of this approach is that the data is serialized and thus saves wire area but also does not require a second higher speed clock to be fed into the serialization circuits and to the wire-pipeline buffers. It should be noted that the employment of serialization in the context of NoC has been proposed to reduce energy consumption [11]. …”