Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

Sk, Gupta; Gupta, Kirti; Calhoun, Benton H.; Pandey, Neeta

doi:10.1109/tcsi.2018.2876785

Cited by 64 publications

(44 citation statements)

References 32 publications

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“…On the other hand, the WWL12T/D12T cell consumes higher area 1.06 × /1.04 × when compared to WALP11T due to the presence of an additional NMOS transistor. Table 1 reports the comparison of the proposed WALP11T cell, in terms of major design metrics, with the previously proposed FD8T [11], BI11T [12], SEDF9T [15], WWL12T [23] and D12T [24] cells as well as additional state-of-the-art SRAM cells such as transmission-gate based 9T (TG9T) [32], power-gated 9T (PG9T) [33], differential writing 10T (10T-P1) [34] and feedback-cutting 11T (FC11T) [35] at V DD = 0.3 V. As is evident, the WALP11T cell shows shorter T RA than most other cells used in this work. However, the FD8T shows shorter T RA than the proposed cell due to its higher β-ratio and its structural similarity to the conventional 6T cell.…”

Section: Layout Areamentioning

confidence: 99%

“…Table 1 reports the comparison of the proposed WALP11T cell, in terms of major design metrics, with the previously proposed FD8T [11], BI11T [12], SEDF9T [15], WWL12T [23] and D12T [24] cells as well as additional state‐of‐the‐art SRAM cells such as transmission‐gate based 9T (TG9T) [32], power‐gated 9T (PG9T) [33], differential writing 10T (10T‐P1) [34] and feedback‐cutting 11T (FC11T) [35] at

V_{DD} = 0.3 normalV

. As is evident, the WALP11T cell shows shorter

T_{RA}

than most other cells used in this work.…”

Section: Comparison Summarymentioning

confidence: 99%

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Reliable write assist low power SRAM cell for wireless sensor network applications

Pal

Bose

et al. 2020

IET Circuits, Devices & Systems

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In this study, the authors have proposed a Write Assist Low Power 11T (WALP11T) SRAM cell. To analyse its performance in terms of major design metrics, the proposed cell has been compared with contemporary SRAMs like the Fully Differential 8T (FD8T), Single-Ended Disturb Free 9T (SEDF9T), Bit-interleaving architecture supporting 11T (BI11T), Selfrefreshing Logic-based 12T (WWL12T) and Differential 12T (D12T) cells. The proposed cell exhibits significantly shorter read/ write delay when compared to most comparison cells. It shows considerably higher read stability and write ability than that of FD8T and SEDF9T/D12T/WWL12T, respectively. Moreover, WALP11T dissipates significantly lower leakage power in comparison to the majority of comparison cells and exhibits 2.21 × /1.18 × lower read power delay product (R PDP) than that of BI11T/D12T and 5.12 × /1.39 × /1.09 × lower write power delay product (W PDP) than that of BI11T/WWL12T/D12T. The proposed cell consumes considerably lower area than WWL12T/D12T and shows highly reliable operation when subjected to the harsh process, voltage and temperature variations at both Slow NMOS-Fast PMOS and Fast NMOS-Slow PMOS corners. For all these improvements, WALP11T shows longer read/write delay than FD8T, higher leakage power and power delay product than BI11T and FD8T/SEDF9T, respectively, at V DD = 0.3 V.

show abstract

Section: Layout Areamentioning

confidence: 99%

V_{DD} = 0.3 normalV

. As is evident, the WALP11T cell shows shorter

T_{RA}

than most other cells used in this work.…”

Section: Comparison Summarymentioning

confidence: 99%

Reliable write assist low power SRAM cell for wireless sensor network applications

Pal

Bose

et al. 2020

IET Circuits, Devices & Systems

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show abstract

“…Many leakage reduction techniques such as super cut‐off CMOS scheme (SSCMOS), dynamic control of power rails in virtually powered read ports, half‐V DD bitline pre‐charge technique, or read‐assist circuits are suggested to address the degraded read performance 2,6,7 . However, their use incurs large area overhead, extra routing efforts, high power consumption, or inefficacy at lower technology nodes 8 . Several SRAM cells with read ports having two to four transistors (2T–4T) are presented in previous studies 8–14 .…”

Section: Introductionmentioning

confidence: 99%

A data‐independent 9T SRAM cell with enhanced I_ON/I_OFF ratio and RBL voltage swing in near threshold and sub‐threshold region

Gupta

Pandey

2021

Circuit Theory & Apps

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Summary The conventional 8T SRAM cell with isolated read port is suggested as an alternative to overcome the read‐write conflicts associated with 6T SRAM cell. However, in near threshold and sub‐threshold regions, 8T cell performance is limited by reduced ION/IOFF ratio, deteriorated RBL voltage swing, data dependency, and higher read failures, although the existing SRAM cells address some of these issues but still suffer from degraded performance due to the trade‐off between leakage and read currents. In this paper, a 9T SRAM cell with novel read port is proposed that aims for low and data‐independent leakages, high ION/IOFF ratio, and large RBL voltage swing in near threshold and sub‐threshold regions. The performance of the proposed cell is compared with 7T, 8T, 9T, and 10T cells at 32 nm technology node by simulating a column of 128 cells to demonstrate its versatility over others. The proposed cell shows enhanced ION/IOFF ratio (71.2X), large RBL voltage swing and data‐independent leakages at VDD = 0.3 V in comparison to the conventional 8T SRAM cell. The results at different PVT corners are also captured to validate the impeccable performance of the proposed cell irrespective of operating conditions.

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“…In 6T SRAM cell, differential bit-line structure increases read and write power dissipation as of single-ended 6T SRAM cell [1]. Single ended SRAM topologies [1,16,[22][23][24] are reported to reduce the power dissipation during read/write operation. P.Singh et al [18] proposed a positive feedback-controlled (PCF10T) SRAM cell with a single ended read operation.…”

Section: Introductionmentioning

confidence: 99%

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

Kumar¹,

Tomar²

2021

Preprint

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This paper presents a single-ended read and differential write half select free 9T static random access memory (SRAM) cell operates in the sub-threshold region. Proposed 9T SRAM cell shows a reasonable reduction in read and write power dissipation by a factor of 1.41× and 2.1× respectively as of conventional 6T (Conv.6T) SRAM cell. The stacking of transistors at core latch network minimizes the leakage power of the cell. The read static noise margin (RSNM) and write margin (WM) are upgraded by 2.16× and 2.06× respectively as of Conv.6T cell. A forward body bias technique is utilized in read path which results to decreases in read access time by a factor of 2.72× as of standard 6T SRAM cell. The mean value of Ion/Ioff ratio of the proposed cell is improved by 2.92× as compared to the Conv.6T SRAM cell. It is attributed to a reduction in bit-line leakage current. To achieve more soundness in characteristics of the proposed 9T SRAM cell, process variation effect on RSNM, power dissipation, and read current is calculated through Monte Carlo (MC) simulation at 5000 points. The obtained results are compared with reference SRAM cells at 0.3V supply voltage.

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Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

Cited by 64 publications

References 32 publications

Reliable write assist low power SRAM cell for wireless sensor network applications

Reliable write assist low power SRAM cell for wireless sensor network applications

A data‐independent 9T SRAM cell with enhanced I_ON/I_OFF ratio and RBL voltage swing in near threshold and sub‐threshold region

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

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Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

Cited by 64 publications

References 32 publications

Reliable write assist low power SRAM cell for wireless sensor network applications

Reliable write assist low power SRAM cell for wireless sensor network applications

A data‐independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub‐threshold region

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

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A data‐independent 9T SRAM cell with enhanced I_ON/I_OFF ratio and RBL voltage swing in near threshold and sub‐threshold region