Low-power linear computation using nonlinear ferroelectric tunnel junction memristors

Berdan, Radu; Marukame, Takao; Ota, Ken‐ichiro; Yamaguchi, Mari; Saitoh, Masumi; Fujii, Shosuke; Deguchi, Jun; Nishi, Yoshifumi

doi:10.1038/s41928-020-0405-0

Cited by 151 publications

(153 citation statements)

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“…The change in the polarization (P) of the ferroelectric domain provides a significant basis for the conductance change of ferroelectric synapses, as shown in Figure 2d. [80][81][82][83][84][85]120] Metals and semiconductors have been used for two-electrode terminals where the two-terminal junction is separated by a ferroelectric layer (e.g., lead zirconate titanate (PZT) and Hf 0.5 Zr 0.5 O 2 (HZO)). [80][81][82][83][84][85]120] The orientation of the P in the ferroelectric material can be aligned differently, depending on the polarity of the external electric field.…”

Section: Ferroelectric Synapsementioning

confidence: 99%

“…[80][81][82][83][84][85]120] Metals and semiconductors have been used for two-electrode terminals where the two-terminal junction is separated by a ferroelectric layer (e.g., lead zirconate titanate (PZT) and Hf 0.5 Zr 0.5 O 2 (HZO)). [80][81][82][83][84][85]120] The orientation of the P in the ferroelectric material can be aligned differently, depending on the polarity of the external electric field. [121,122] The modulation of P for a metal/ferroelectric layer/semiconductor (MFS) junction can alter the junction resistance, which might be attributed to asymmetric screening effects at the interfaces between the metal/ferroelectric and the semiconductor/ferroelectric layers.…”

Section: Ferroelectric Synapsementioning

confidence: 99%

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Emerging Memristive Artificial Synapses and Neurons for Energy‐Efficient Neuromorphic Computing

2020

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as the thermal budget has increased rapidly in recent years, which could surpass the future revenue generated worldwide by the semiconductor industry. [4,5] Consequently, electronic miniaturization limits the sustainable growth of computing technology. The von Neumann design is a conventional computing architecture, which separates the processor and memory unit. This architecture performs a computational task through sequential procedures and has functioned a mainstay of modern computing since 1945. [6] In fact, the architecture is significantly beneficial to both hardware and software developers because each component can be improved and readily extended into a united electronic system, even without a comprehensive understanding of all the components. However, the von Neumann bottleneck generates substantial power consumption and latency during the computing operation. [2,7] This limitation results from data transmission between two functional units (processor and memory), particularly when the memory is accessed through a bus with restricted bandwidth. [2,7] Moreover, according to the International Data Corporation (IDC), global data will rapidly increase to 175 ZB (1.75 × 10 23 B) by 2025. [8] Consequently, the von Neumann bottleneck will be more detrimental under tremendous workload because it may be produced by the daily operation of the design. Recently, there has been increasing demand for intellectual computers that can efficiently process substantial global data, thereby resulting in the development of a wide range of softwareor hardware-based artificial neural networks (ANNs) aimed at achieving the computing ability of the human brain. [2,9] Softwarebased ANNs have recently exhibited remarkable capabilities, such as image recognition, [10,11] natural language processing, [12,13] and performing specific tasks, [14] some beyond the human level. However, since existing ANNs are built on conventional computing architecture, that is, the von Neumann architecture, the learning parameters stored in memory are iteratively introduced to the processor to perform a task. The bottleneck issue arising from the movement of large datasets would eventually reduce the energy and time efficiency when operating the ANN software. [2,7] To alleviate this problem, several advanced software-and hardware-based ANN approaches have been suggested. [2,7,15-17] Advanced algorithms, such as network pruning, quantization, Huffman coding, and knowledge distillation, have been Memristors have recently attracted significant interest due to their applicability as promising building blocks of neuromorphic computing and electronic systems. The dynamic reconfiguration of memristors, which is based on the history of applied electrical stimuli, can mimic both essential analog synaptic and neuronal functionalities. These can be utilized as the node and terminal devices in an artificial neural network. Consequently, the ability to understand, control, and utilize fundamental switching principles and various types of device architectures of the...

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Section: Ferroelectric Synapsementioning

confidence: 99%

Section: Ferroelectric Synapsementioning

confidence: 99%

Emerging Memristive Artificial Synapses and Neurons for Energy‐Efficient Neuromorphic Computing

2020

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“…Performance CMOS technology [35] This work [36] Speed 2.29 ns 780 ns 195 ps [37] Figure 7. The output current results with different resistance variations.…”

Section: Performance Evaluation Of Hw Calculationmentioning

confidence: 99%

In‐Memory Hamming Weight Calculation in a 1T1R Memristive Array

Cheng

Zheng

et al. 2020

Adv Elect Materials

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In‐memory computing enabled by advanced nonvolatile memory technologies, such as memristors and memristive devices, emerges as a promising approach to accelerate certain data‐intensive algorithms, and thus outperforms the von Neumann computing in terms of processing latency and energy efficiency. In this work, an efficient method to calculate the Hamming weight (HW) of a binary string in a one‐transistor‐one‐resistor (1T1R) memristive array is proposed, which can be beneficial for various computation tasks. Specifically, the target string is converted to a voltage vector and multiplies with an “all‐1” string pre‐stored in the resistance of the row, which equals to a binary matrix multiplication or AND logic operation. The in situ stored HW calculation result is then read out through a current accumulation operation. As a proof‐of‐concept demonstration, 4 bit and 8 bit HW calculation is successfully implemented in experiment and simulation, respectively. In addition, the influence of the resistance variation on the calculation correctness is discussed. This work broadens the application range of using emerging nonvolatile memories for classical information processing in hardware level with high efficiency.

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“…Another challenge is the difficulty of synthesising large-area vdW ferroelectric films, which limits the scaling up potential of vdW FTJs. Nevertheless, with the establishment of new programming schemes 9 , we expect that vdW FTJs will prove to be of value in the development of highly energy-efficient data storage and in-memory computing. ❐ Xinran Published online: 5 August 2020 https://doi.org/10.1038/s41928-020-0463-3…”

Section: Ferroelectric Tunnel Junctions With High Tunnelling Electrormentioning

confidence: 99%

Ferroelectric tunnel junctions with high tunnelling electroresistance

Wang

2020

Nat Electron

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Low-power linear computation using nonlinear ferroelectric tunnel junction memristors

Cited by 151 publications

References 43 publications

Emerging Memristive Artificial Synapses and Neurons for Energy‐Efficient Neuromorphic Computing

Emerging Memristive Artificial Synapses and Neurons for Energy‐Efficient Neuromorphic Computing

In‐Memory Hamming Weight Calculation in a 1T1R Memristive Array

Ferroelectric tunnel junctions with high tunnelling electroresistance

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