Low-Power K/Q-Band Digital Phased Array Chiplet

Hornbuckle, Craig; Mrozek, Eric; Krawczyk, T.W.; Lugthart, Marcel

doi:10.1109/past49659.2022.9975074

Cited by 1 publication

(1 citation statement)

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“…Furthermore, an ADC demonstrated operation at 12 Gb/s with 12 bits of data, for a total data rate of 144 Gb/s. 10,11 Using the parallelization of a chiplet HI interface, these data are offloaded to the signal processing chip in 32 12-bit channels operating at 375 Mb/s. These types of data rates will be required for future radar and 6G communication.…”

Section: Microelectronicsmentioning

confidence: 99%

Exploring Heterogeneous Integration: Its Essence and Future Path

Nordquist,

Chou

2024

Computer

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Heterogeneous integration (HI) is the integration of chiplets using packaging technologies. Whereas a traditional system on chip (SoC) uses semiconductor technologies to integrate functionalities on a single silicon wafer, HI looks to disaggregate the functionalities of a SoC into smaller chiplets, or use proven intellectual properties (IPs) and older technologies and repackage them into a new product built for specific applications. This approach of producing a system in package (SiP) has proven attractive, especially as the progress of Moore's law has waned. Indeed, for the bulk of our lifetime, Moore's law has allowed transistor densities to double every two years. This fueled the integration of increasingly complex functionalities into a single silicon chip and the aggregation of multiple functionalities, including the CPU, graphics processing, custom accelerators, memor y, and input-output functionalities. However, as the transistor integration approaches billions per chip, the economic and technological drivers are steering manufacturers away from monolithic integration. Here, as monolithic chip sizes swell to the size of a reticle, the yield of a monolithic SoC falls appreciably because of defects in the semiconductor manufacturing process. Consequently,

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Section: Microelectronicsmentioning

confidence: 99%