Exploring Heterogeneous Integration: Its Essence and Future Path

Abstract

Heterogeneous integration (HI) is the integration of chiplets using packaging technologies. Whereas a traditional system on chip (SoC) uses semiconductor technologies to integrate functionalities on a single silicon wafer, HI looks to disaggregate the functionalities of a SoC into smaller chiplets, or use proven intellectual properties (IPs) and older technologies and repackage them into a new product built for specific applications. This approach of producing a system in package (SiP) has proven attractive, especially as the progress of Moore's law has waned. Indeed, for the bulk of our lifetime, Moore's law has allowed transistor densities to double every two years. This fueled the integration of increasingly complex functionalities into a single silicon chip and the aggregation of multiple functionalities, including the CPU, graphics processing, custom accelerators, memor y, and input-output functionalities. However, as the transistor integration approaches billions per chip, the economic and technological drivers are steering manufacturers away from monolithic integration. Here, as monolithic chip sizes swell to the size of a reticle, the yield of a monolithic SoC falls appreciably because of defects in the semiconductor manufacturing process. Consequently,