Low Power Implementation of Trivium Stream Cipher

Mora, J.M.; Jimenez-Fernandez, C. J.; Barrero, Manuel

doi:10.1007/978-3-642-36157-9_12

Cited by 8 publications

(12 citation statements)

References 6 publications

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“…This, however, required additional modifications in the structure of the Trivium, as discussed in [17]. This, however, required additional modifications in the structure of the Trivium, as discussed in [17].…”

Section: Full-parallel Low-power Triviummentioning

confidence: 99%

“…In the FPLP implementation, the parallelization technique was applied to all the flip-flops in the shift registers. This, however, required additional modifications in the structure of the Trivium, as discussed in [17].…”

Section: Full-parallel Low-power Triviummentioning

confidence: 99%

“…It is difficult to compare power consumption in the different Trivium implementations because the technologies used are different, despite their identical transistor sizes. If frequency and voltage in the 130-nm technology are scaled up, for example, the FPLP Trivium implementation [17] can be seen to have lower cell dynamic power consumption than the implementation described in [12,13]. For the 350-nm technology, however, comparison is more difficult, not only because the technologies are different, but also because the low-power Trivium implemented in [15] is radix-16 and uses a reduced effective clock frequency, making scaling more indeterminate.…”

Section: Comparison Between Mixed-parallel Low-power and Full-parallementioning

confidence: 99%

“…This alternative was applied in an earlier study [17] in which good results were obtained for a Trivium even though only results from logical simulations were presented. The first alternative was the mixed-parallel low-power (MPLP) Trivium implementation, where parallelization was applied to flip-flops unaffected by nonlinear feedback paths.…”

Section: Introductionmentioning

confidence: 99%

“…The second was the full-parallel low-power (FPLP) implementation, where the parallelization technique was applied to all the flip-flops in the Trivium stream cipher, even though this meant redesigning non-linear feedback paths. This alternative was applied in an earlier study [17] in which good results were obtained for a Trivium even though only results from logical simulations were presented. That low-power implementation of Trivium was improved and updated to the FPLP version.…”

Section: Introductionmentioning

confidence: 99%

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Trivium hardware implementations for power reduction

Mora

Jimenez-Fernandez

Barrero

2016

Circuit Theory & Apps

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This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology with both transistors and gate-level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area.

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Section: Full-parallel Low-power Triviummentioning

confidence: 99%

Section: Full-parallel Low-power Triviummentioning

confidence: 99%

Section: Comparison Between Mixed-parallel Low-power and Full-parallementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Trivium hardware implementations for power reduction

Mora

Jimenez-Fernandez

Barrero

2016

Circuit Theory & Apps

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Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview

Acosta

Addabbo

Tena-Sánchez

2016

Circuit Theory & Apps

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We provide an overview of selected crypto-hardware devices, with a special reference to the lightweight electronic implementation of encryption/decryption schemes, hash functions, and true random number generators. In detail, we discuss the hardware implementation of the chief algorithms used in private-key cryptography, public-key cryptography, and hash functions, discussing some important security issues in electronic crypto-devices, related to side-channel attacks (SCAs), fault injection attacks, and the corresponding design countermeasures that can be taken. Finally, we present an overview about the hardware implementation of true random number generators, discussing the chief electronic sources of randomness and the types of post-processing techniques used to improve the statistical characteristics of the generated random sequences.A. J. ACOSTA, T. ADDABBO AND E. TENA-SÁNCHEZ resource consumption. This matter sets the point for the lightweight cryptography, that is, the subfield of cryptography aiming to provide solutions tailored for resource-constrained devices.According to Elsevier Scopus, the largest database of research peer-reviewed literature, since 2010, about 40k documents are returned if searching the keyword 'cryptography' [6]. A huge subset of these papers deals with conceptual, algorithmic, software, hardware solutions that may be taken into account in lightweight cryptography. In the face of such a vast literature, in this work, we provide a brief overview of selected crypto-hardware devices, with a special reference to the lightweight electronic implementation of encryption/decryption schemes, hash functions, and true random number generators (TRNGs).This paper is organized as in the following. In Section 2, we introduce some terminology and present an overview of the hardware implementation of the chief algorithms used in private-key cryptography, public-key cryptography (PKC), and hash functions. In Sections 3 and 4, we introduce some important security concerns about electronic crypto-devices, discussing SCAs, fault injection attacks, and the corresponding countermeasures that can be taken in the hardware design. Finally, Sections 5-8 are devised to provide an overview about the electronic implementation of TRNGs. In detail, in Sections 5 and 6, we discuss about security flaws, statistical defects, and predictability of TRNGs, presenting the chief sources of randomness used nowadays for their hardware implementation. In Sections 7 and 8, we discuss an overview of the different post-processing techniques aimed to improve the statistical characteristics of the generated random sequences and the evaluation methods used to assess the reliability of cryptographic TRNGs. Conclusion and References close the paper. CRYPTOGRAPHIC ALGORITHMSCryptographic algorithms aim to convert secret data into an unreadable code for non authorized persons, protecting secret information from theft or alteration and also enabling authentication. For better understanding, in the next sections, we define the following...

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